IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

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Volume E88-A No.12  (Publication Date:2005/12/01)
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Special Section on VLSI Design and CAD Algorithms

pp.3273-3273  FOREWORD
FOREWORD
Shinji KIMURA  
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pp.3274-3281  PAPER-Low Power Methodology
Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy
Hidekazu TANAKA  Koji INOUE  
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pp.3282-3289  PAPER-Low Power Methodology
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications
Satoshi KOMATSU  Masahiro FUJITA  
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pp.3290-3297  PAPER-Low Power Methodology
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era
Kentaro KAWAKAMI  Miwako KANAMORI  Yasuhiro MORITA  Jun TAKEMURA  Masayuki MIYAMA  Masahiko YOSHIMOTO  
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pp.3298-3305  PAPER-Low Power Methodology
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages
Weisheng CHONG  Masanori HARIYAMA  Michitaka KAMEYAMA  
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pp.3306-3314  PAPER-Simulation and Verification
Trace-Driven Performance Simulation Modeling for Fast Evaluation of Multimedia Processor by Simulation Reuse
Ho Young KIM  Tag Gon KIM  
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pp.3315-3323  PAPER-Simulation and Verification
An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences
Takeshi MATSUMOTO  Hiroshi SAITO  Masahiro FUJITA  
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pp.3324-3331  PAPER-Logic Synthesis
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition
Masao MORIMOTO  Yoshinori TANAKA  Makoto NAGATA  Kazuo TAKI  
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pp.3332-3341  PAPER-Logic Synthesis
Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs
Debatosh DEBNATH  Tsutomu SASAO  
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pp.3342-3350  PAPER-Logic Synthesis
A Design Algorithm for Sequential Circuits Using LUT Rings
Hiroki NAKAHARA  Tsutomu SASAO  Munehiro MATSUURA  
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pp.3351-3357  PAPER-Logic Synthesis
An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs
Yuichi NAKAMURA  Ko YOSHIKAWA  Takeshi YOSHIMURA  
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pp.3358-3366  PAPER-Prediction and Analysis
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model
Hidenari NAKASHIMA  Junpei INOUE  Kenichi OKADA  Kazuya MASU  
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pp.3367-3374  PAPER-Prediction and Analysis
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Zhangcai HUANG  Atsushi KUROKAWA  Jun PAN  Yasuaki INOUE  
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pp.3375-3381  PAPER-Prediction and Analysis
Statistical Analysis of Clock Skew Variation in H-Tree Structure
Masanori HASHIMOTO  Tomonori YAMAMOTO  Hidetoshi ONODERA  
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pp.3382-3389  PAPER-Prediction and Analysis
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
Takashi SATO  Junji ICHIMIYA  Nobuto ONO  Koutaro HACHIYA  Masanori HASHIMOTO  
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pp.3390-3397  PAPER-Floorplan and Placement
A Graph Based Soft Module Handling in Floorplan
Hiroaki ITOGA  Chikaaki KODAMA  Kunihiro FUJIYOSHI  
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pp.3398-3404  PAPER-Floorplan and Placement
An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation
Jing LI  Juebang YU  Hiroshi MIYASHITA  
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pp.3405-3411  PAPER-Floorplan and Placement
Navigating Register Placement for Low Power Clock Network Design
Yongqiang LU  Chin-Ngai SZE  Xianlong HONG  Qiang ZHOU  Yici CAI  Liang HUANG  Jiang HU  
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pp.3412-3420  PAPER-Power/Ground Network
Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm
Yun YANG  Atsushi KUROKAWA  Yasuaki INOUE  Wenqing ZHAO  
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pp.3421-3428  PAPER-Power/Ground Network
Power-Supply Noise Reduction with Design for Manufacturability
Hiroyuki TSUJIKAWA  Kenji SHIMAZAKI  Shozo HIRANO  Kazuhiro SATO  Masanori HIROFUJI  Junichi SHIMADA  Mitsumi ITO  Kiyohito MUKAI  
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pp.3429-3436  PAPER-Power/Ground Network
Successive Pad Assignment for Minimizing Supply Voltage Drop
Takashi SATO  Masanori HASHIMOTO  Hidetoshi ONODERA  
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pp.3437-3444  PAPER-Interconnect
Evaluation of X Architecture Using Interconnect Length Distribution
Hidenari NAKASHIMA  Naohiro TAKAGI  Junpei INOUE  Kenichi OKADA  Kazuya MASU  
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pp.3445-3452  PAPER-Interconnect
Wire Length Distribution Model for System LSI
Takanori KYOGOKU  Junpei INOUE  Hidenari NAKASHIMA  Takumi UEZONO  Kenichi OKADA  Kazuya MASU  
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pp.3453-3462  PAPER-Interconnect
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance
Atsushi KUROKAWA  Masanori HASHIMOTO  Akira KASEBE  Zhangcai HUANG  Yun YANG  Yasuaki INOUE  Ryosuke INAGAKI  Hiroo MASUDA  
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pp.3463-3470  PAPER-Interconnect
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Toshiki KANAMOTO  Tetsuya WATANABE  Mitsutoshi SHIROTA  Masayuki TERAI  Tatsuya KUNIKIYO  Kiyoshi ISHIKAWA  Yoshihide AJIOKA  Yasutaka HORIBA  
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pp.3471-3478  PAPER-Interconnect
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills
Atsushi KUROKAWA  Toshiki KANAMOTO  Tetsuya IBE  Akira KASEBE  Wei Fong CHANG   Tetsuro KAGE  Yasuaki INOUE  Hiroo MASUDA  
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pp.3479-3484  PAPER-Circuit Synthesis
On the Computational Synthesis of CMOS Voltage Followers
Esteban TLELO-CUAUTLE  Delia TORRES-MUÑOZ  Leticia TORRES-PAPAQUI  
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pp.3485-3491  PAPER-Circuit Synthesis
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells
Tetsuya IIZUKA  Makoto IKEDA  Kunihiro ASADA  
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pp.3492-3499  PAPER-VLSI Architecture
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application
Yuichiro MURACHI  Koji HAMANO  Tetsuro MATSUNO  Junichi MIYAKOSHI  Masayuki MIYAMA  Masahiko YOSHIMOTO  
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pp.3500-3507  PAPER-VLSI Architecture
Quality and Power Efficient Architecture for the Discrete Cosine Transform
Chi-Chia SUNG  Shanq-Jang RUAN  Bo-Yao LIN  Mon-Chau SHIE  
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pp.3508-3515  PAPER-VLSI Architecture
VLSI Implementation of Lifting Wavelet Transform of JPEG2000 with Efficient RPA(Recursive Pyramid Algorithm) Realization
Gab-Cheon JUNG  Seong-Mo PARK  
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pp.3516-3522  PAPER-VLSI Architecture
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture
Masanori HARIYAMA  Yasuhiro KOBAYASHI  Haruka SASAKI  Michitaka KAMEYAMA  
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pp.3523-3530  PAPER-VLSI Architecture
A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation
Zhenyu LIU  Yang SONG  Takeshi IKENAGA  Satoshi GOTO  
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pp.3531-3538  PAPER-VLSI Architecture
A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)
Yuan-Long JEANG  Jer-Min JOU  Win-Hsien HUANG  
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pp.3539-3547  PAPER-VLSI Architecture
High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes
Luca FANUCCI  Massimo ROVINI  Nicola E. L'INSALATA  Francesco ROSSI  
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pp.3548-3553  PAPER-VLSI Circuit
Multiplier Energy Reduction by Dynamic Voltage Variation
Vasily G. MOSHNYAGA  Tomoyuki YAMANAKA  
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pp.3554-3563  PAPER-VLSI Circuit
A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting
Pao-Lung CHEN  Chen-Yi LEE  
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pp.3564-3572  LETTER
Effects of On-Chip Inductance on Power Distribution Grid
Atsushi MURAMATSU  Masanori HASHIMOTO  Hidetoshi ONODERA  
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pp.3573-3576  LETTER
Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions
Chia-Chi CHU  Ming-Hong LAI  Wu-Shiung FENG  
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pp.3577-3579  LETTER
A Simplified Illustration of Arbitrary DAC Waveform Effects in Continuous Time Delta-Sigma Modulators
Hossein SHAMSI  Omid SHOAEI  
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pp.3580-3583  LETTER
Frequency-Scaling Approach for Managing Power Consumption in NOCs
Chun-Lung HSU  Wen-Tso WANG  Ying-Fu HONG  
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Regular Section

pp.3584-3592  PAPER-Engineering Acoustics
Development of Sound Localization System with Tube Earphone Using Human Head Model with Ear Canal
Marie NAKAZAWA  Atsuhiro NISHIKATA  
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pp.3593-3603  PAPER-Engineering Acoustics
Subband-Based Blind Separation for Convolutive Mixtures of Speech
Shoko ARAKI  Shoji MAKINO  Robert AICHNER  Tsuyoki NISHIKAWA  Hiroshi SARUWATARI  
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pp.3604-3609  PAPER-Systems and Control
Global Asymptotic Stabilization of a Class of Nonlinear Time-Delay Systems by Output Feedback
Ho-Lim CHOI  Jong-Tae LIM  
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pp.3610-3617  PAPER-VLSI Design Technology and CAD
A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm
Marcelo E. KAIHARA  Naofumi TAKAGI  
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pp.3618-3626  PAPER-Reliability, Maintainability and Safety Analysis
Bayesian Approach to Optimal Release Policy of Software System
HeeSoo KIM  Shigeru YAMADA  DongHo PARK  
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pp.3627-3635  PAPER-Coding Theory
Some Classes of Quasi-Cyclic LDPC Codes: Properties and Efficient Encoding Method
Hachiro FUJITA  Kohichi SAKANIWA  
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pp.3636-3644  PAPER-Spread Spectrum Technologies and Applications
Bounds on Aperiodic Autocorrelation and Crosscorrelation of Binary LCZ/ZCZ Sequences
Daiyuan PENG  Pingzhi FAN  Naoki SUEHIRO  
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pp.3645-3653  PAPER-Neural Networks and Bioengineering
Avoiding the Local Minima Problem in Backpropagation Algorithm with Modified Error Function
Weixing BI  Xugang WANG  Zheng TANG  Hiroki TAMURA  
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pp.3654-3657  LETTER-Digital Signal Processing
On Linear Least Squares Approach for Phase Estimation of Real Sinusoidal Signals
Hing-Cheung SO  
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pp.3658-3660  LETTER-Systems and Control
On the Property of a Discrete Impulse Response Gramian with Application to Model Reduction
Younseok CHOO  
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pp.3661-3662  LETTER-Graphs and Networks
A Note on the Implementation of de Bruijn Networks by the Optical Transpose Interconnection System
Kohsuke OGATA  Toshinori YAMADA  Shuichi UENO  
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pp.3663-3667  LETTER-Information Security
Stego-Encoding with Error Correction Capability
Xinpeng ZHANG  Shuozhong WANG  
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pp.3668-3671  LETTER-Information Security
Complexity of Differential Attacks on SHA-0 with Various Message Schedules
Mitsuhiro HATTORI  Shoichi HIROSE  Susumu YOSHIDA  
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pp.3672-3674  LETTER-Coding Theory
A Step-by-Step Implementation Method of the Bit-Serial Reed-Solomon Encoder
Jinsoo BAE  Hiroyuki MORIKAWA  
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pp.3675-3676  LETTER-Coding Theory
Properties of m-Sequence and Construction of Constant Weight Codes
Fanxin ZENG  
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pp.3677-3680  LETTER-General Fundamentals and Boundaries
An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications
Jaesang LIM  Yongchul SONG  Jeongpyo KIM  Beomsup KIM  
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