IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

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Volume E87-A No.12  (Publication Date:2004/12/01)
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Special Section on VLSI Design and CAD Algorithms

pp.3029-3029  FOREWORD
FOREWORD
Michiaki MURAOKA  
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pp.3030-3035  PAPER-System Level Design
RTOS-Centric Cosimulator for Embedded System Design
Shinya HONDA  Takayuki WAKABAYASHI  Hiroyuki TOMIYAMA  Hiroaki TAKADA  
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pp.3036-3046  PAPER-System Level Design
FPGA-Based Reconfigurable Adaptive FEC
Kazunori SHIMIZU  Jumpei UCHIDA  Yuichiro MIYAOKA  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3047-3056  PAPER-System Level Design
An IP Synthesizer for Limited-Resource DWT Processor
Lan-Rong DUNG  
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pp.3057-3067  PAPER-System Level Design
SoC Architecture Synthesis Methodology Based on High-Level IPs
Michiaki MURAOKA  Hiroaki NISHI  Rafael K. MORIZAWA  Hideaki YOKOTA  Yoichi ONISHI  
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pp.3068-3074  PAPER-System Level Design
An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU
Fumio ARAKAWA  Motokazu OZAWA  Osamu NISHII  Toshihiro HATTORI  Takeshi YOSHINAGA  Tomoichi HAYASHI  Yoshikazu KIYOSHIGE  Takashi OKADA  Masakazu NISHIBORI  Tomoyuki KODAMA  Tatsuya KAMEI  Makoto ISHIKAWA  
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pp.3075-3082  PAPER-System Level Design
High-Level Power Optimization Based on Thread Partitioning
Jumpei UCHIDA  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3083-3090  PAPER-System Level Design
Coupling-Driven Data Bus Encoding for SoC Video Architectures
Luca FANUCCI  Riccardo LOCATELLI  Andrea MINGHI  
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pp.3091-3099  PAPER-System Level Design
Power Modeling of Synthesizable Soft Macros
Kyung Tae DO  Yang Hyo KIM  Young Hwan KIM  Jung Yun CHOI  
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pp.3100-3108  PAPER-Logic Synthesis
On Multiple-Voltage High-Level Synthesis Using Algorithmic Transformations
Lan-Rong DUNG  Hsueh-Chih YANG  
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pp.3109-3115  PAPER-Logic Synthesis
A Low-Power Architecture for Extended Finite State Machines Using Input Gating
Shi-Yu HUANG  Chien-Jyh LIU  
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pp.3116-3123  PAPER-Logic Synthesis
Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power
Kimiyoshi USAMI  Hiroshi YOSHIOKA  
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pp.3124-3133  PAPER-Logic Synthesis
Super-Set of Permissible Functions and Its Application to the Transduction Method
Katsunori TANAKA  Yahiko KAMBAYASHI  
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pp.3134-3140  PAPER-Logic Synthesis
Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form
Debatosh DEBNATH  Tsutomu SASAO  
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pp.3141-3150  PAPER-Logic Synthesis
A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN  Tsutomu SASAO  Munehiro MATSUURA  Shinobu NAGAYAMA  Kazuyuki NAKAMURA  Yukihiro IGUCHI  
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pp.3151-3158  PAPER-Logic Synthesis
Timing Optimization Methodology Based on Replacing Flip-Flops by Latches
Ko YOSHIKAWA  Keisuke KANAMARU  Yasuhiko HAGIHARA  Shigeto INUI  Yuichi NAKAMURA  Takeshi YOSHIMURA  
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pp.3159-3165  PAPER-Logic Synthesis
Efficient False Aggressors Pruning with Functional Correlation
Hyungwoo LEE  Juho KIM  
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pp.3166-3173  PAPER-Logic Synthesis
A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains
Suk-Jin KIM  Jeong-Gun LEE  Kiseon KIM  
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pp.3174-3184  PAPER-Test
Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints
Makoto SUGIHARA  Kazuaki MURAKAMI  Yusuke MATSUNAGA  
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pp.3185-3192  PAPER-Test
Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories
Jin-Fu LI  
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pp.3193-3199  PAPER-Test
A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs
Youhua SHI  Shinji KIMURA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3200-3207  PAPER-Test
A Design Scheme for Delay Testing of Controllers Using State Transition Information
Tsuyoshi IWAGAKI  Satoshi OHTAKE  Hideo FUJIWARA  
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pp.3208-3215  PAPER-Test
A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction
Youhua SHI  Shinji KIMURA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3216-3223  PAPER-Test
Synthesis for Testability of Synchronous Sequential Circuits with Strong-Connectivity Using Undefined States on State Transition Graph
Soo-Hyun KIM  Ho-Yong CHOI  Kiseon KIM  Dong-Ik LEE  
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pp.3224-3232  PAPER-Floorplan
Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints
Ning FU  Shigetoshi NAKATAKE  Yasuhiro TAKASHIMA  Yoji KAJITANI  
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pp.3233-3243  PAPER-Floorplan
EQ-Sequences for Coding Floorplans
Hua-An ZHAO  Chen LIU  Yoji KAJITANI  Keishi SAKANUSHI  
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pp.3244-3250  PAPER-Floorplan
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI
Kazuki FUKUOKA  Masaaki IIJIMA  Kenji HAMADA  Masahiro NUMA  Akira TADA  
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pp.3251-3257  PAPER-Physical Design
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Masanori HASHIMOTO  Hidetoshi ONODERA  
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pp.3258-3264  PAPER-Physical Design
A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects
Keiji KIDA  Xiaoke ZHU  Changwen ZHUANG  Yasuhiro TAKASHIMA  Shigetoshi NAKATAKE  
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pp.3265-3272  PAPER-Physical Design
Partial Random Walks for Transient Analysis of Large Power Distribution Networks
Weikun GUO  Sheldon X.-D. TAN  Zuying LUO  Xianlong HONG  
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pp.3273-3280  PAPER-Physical Design
A Fast Decoupling Capacitor Budgeting Algorithm for Robust On-Chip Power Delivery
Jingjing FU  Zuying LUO  Xianlong HONG  Yici CAI  Sheldon X.-D. TAN  Zhu PAN  
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pp.3281-3292  PAPER-Physical Design
Applications of Tree/Link Partitioning for Moment Computations of General Lumped R(L)C Interconnect Networks with Multiple Resistor Loops
Herng-Jer LEE  Ming-Hong LAI  Chia-Chi CHU  Wu-Shiung FENG  
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pp.3293-3300  PAPER-Physical Design
High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability
Tetsuya IIZUKA  Makoto IKEDA  Kunihiro ASADA  
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pp.3301-3308  PAPER-Analog Layout
A Device-Level Placement with Schema Based Clusters in Analog IC Layouts
Takashi NOJIMA  Xiaoke ZHU  Yasuhiro TAKASHIMA  Shigetoshi NAKATAKE  Yoji KAJITANI  
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pp.3309-3317  PAPER-Device Modeling
Automatic Extraction of Layout-Dependent Substrate Effects for RF MOSFET Modeling
Zhao LI  Ravikanth SURAVARAPU  Kartikeya MAYARAM  C.-J. Richard SHI  
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pp.3318-3323  LETTER-Test
Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs
Kazumi HATAYAMA  Michinobu NAKAO  Yoshikazu KIYOSHIGE  Koichiro NATSUME  Yasuo SATO  Takaharu NAGUMO  
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pp.3324-3326  LETTER-Physical Design
A Novel Digitally-Controlled Varactor for Portable Delay Cell Design
Pao-Lung CHEN  Ching-Che CHUNG  Chen-Yi LEE  
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Regular Section

pp.3327-3333  PAPER-Digital Signal Processing
Design of High-Order Noise-Shaping FIR Filters for Overload-Free Stable Single- and Multi-Bit Data Converters
Mitsuhiko YAGYU  Akinori NISHIHARA  
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pp.3334-3342  PAPER-Digital Signal Processing
Progressive Coding of Binary Voxel Models Based on Pattern Code Representation
Bong Gyun ROH  Chang-Su KIM  Sang-Uk LEE  
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pp.3343-3349  PAPER-Digital Signal Processing
Blind Source Separation Based on Phase and Frequency Redundancy of Cyclostationary Signals
Yong XIANG  Wensheng YU  Jingxin ZHANG  Senjian AN  
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pp.3350-3359  PAPER-Digital Signal Processing
Fixed-Point, Fixed-Interval and Fixed-Lag Smoothing Algorithms from Uncertain Observations Based on Covariances
Seiichi NAKAMORI  Raquel CABALLERO-AGUILA  Aurora HERMOSO-CARAZO  Josefa LINARES-PEREZ  
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pp.3360-3371  PAPER-Digital Signal Processing
A Practical Subspace Blind Identification Algorithm with Reduced Computational Complexity
Nari TANABE  Toshihiro FURUKAWA  Kohichi SAKANIWA  Shigeo TSUJII  
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pp.3372-3380  PAPER-Systems and Control
T-S Fuzzy Model-Based Synchronization of Time-Delay Chaotic System with Input Saturation
Jae-Hun KIM  Hyunseok SHIN  Euntai KIM  Mignon PARK  
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pp.3381-3388  PAPER-Nonlinear Problems
A Statistical Analysis of Non-linear Equations Based on a Linear Combination of Generalized Moments
Hideki SATOH  
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pp.3389-3396  PAPER-Reliability, Maintainability and Safety Analysis
Maximum Likelihood Analysis of Masked Data in Competing Risks Models with an Environmental Stress
Yoshimitsu NAGAI  
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pp.3397-3403  PAPER-Communication Theory and Signals
Derivation on Bit Error Probability of Coded QAM Using Integer Codes
Hristo KOSTADINOV  Hiroyoshi MORITA  Nikolai MANEV  
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pp.3404-3408  PAPER-Image
A New Feature Extraction for Iris Identification Using Scale-Space Filtering Technique
Jinil HONG  Woo Suk YANG  Dongmin KIM  Young-Ju KIM  
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pp.3409-3419  PAPER-Image
Analysis and Evaluation of Required Precision for Color Images in Digital Cinema Application
Junji SUZUKI  Isao FURUKAWA  Sadayasu ONO  
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pp.3420-3423  PAPER-General Fundamentals and Boundaries
A View on the Fourier Integrals and Related Delta Function
Yoshihiko AKAIWA  
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pp.3424-3428  LETTER-Digital Signal Processing
Effect of Time Division on Estimation Accuracy in Frequency Domain ICA
Yasunari YOKOTA  Hideaki IWATA  Motoki SHIGA  
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pp.3429-3432  LETTER-Digital Signal Processing
A Construction of Low-Peak-Factor Pseudo White Noise
Takafumi HAYASHI  
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pp.3433-3435  LETTER-Analog Signal Processing
Digital Calibration Techniques for Pipelined ADCs
Jeongpyo KIM  Yongchul SONG  Beomsup KIM  
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pp.3436-3438  LETTER-Systems and Control
State Dependent Dwell Time Switching for Discrete-Time Stable Systems
Jung-Su KIM  Tae-Woong YOON  Claudio DE PERSIS  
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pp.3439-3442  LETTER-Systems and Control
Solutions of Takagi-Sugeno Fuzzy-Model-Based Dynamic Equations via Orthogonal Functions
Wen-Hsien HO  Jyh-Horng CHOU  
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pp.3443-3446  LETTER-Information Security
Security Notes on Generalization of Threshold Signature and Authenticated Encryption
Shuhong WANG  Guilin WANG  Feng BAO  Jie WANG  
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pp.3447-3451  LETTER-Spread Spectrum Technologies and Applications
Performance of Cellular CDMA Systems Using SBF and TBF Array Antennas under Multi-Cell Environment
Hyunduk KANG  Insoo KOO  Vladimir KATKOVNIK  Kiseon KIM  
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