IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

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Volume E86-A No.12  (Publication Date:2003/12/01)
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Special Section on VLSI Design and CAD Algorithms

pp.2913-2913  FOREWORD
FOREWORD
Masaharu IMAI  
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pp.2914-2922  PAPER-Parasitics and Noise
Statistical Gate-Delay Modeling with Intra-Gate Variability
Kenichi OKADA  Kento YAMAOKA  Hidetoshi ONODERA  
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pp.2923-2932  PAPER-Parasitics and Noise
Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays
Sadahiro TANI  Yoshihiro UCHIDA  Makoto FURUIE  Shuji TSUKIYAMA  BuYeol LEE  Shuji NISHI  Yasushi KUBOTA  Isao SHIRAKAWA  Shigeki IMAI  
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pp.2933-2941  PAPER-Parasitics and Noise
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
Atsushi KUROKAWA  Takashi SATO  Hiroo MASUDA  
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pp.2942-2951  PAPER-Parasitics and Noise
Representative Frequency for Interconnect R(f)L(f)C Extraction
Akira TSUCHIYA  Masanori HASHIMOTO  Hidetoshi ONODERA  
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pp.2952-2964  PAPER-Parasitics and Noise
Moment Computations of Lumped Coupled RLC Trees with Applications to Estimating Crosstalk Noise
Herng-Jer LEE  Chia-Chi CHU  Wu-Shiung FENG  
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pp.2965-2973  PAPER-Parasitics and Noise
Crosstalk Noise Estimation for Generic RC Trees
Masanori HASHIMOTO  Masao TAKAHASHI  Hidetoshi ONODERA  
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pp.2974-2982  PAPER-Parasitics and Noise
A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation
Hiroyuki TSUJIKAWA  Shozo HIRANO  Kenji SHIMAZAKI  
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pp.2983-2990  PAPER-Power Optimization
Variable Pipeline Depth Processor for Energy Efficient Systems
Akihiko HYODO  Masanori MUROYAMA  Hiroto YASUURA  
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pp.2991-3000  PAPER-Power Optimization
A Low Power Embedded DRAM Macro for Battery-Operated LSIs
Takeshi FUJINO  Akira YAMAZAKI  Yasuhiko TAITO  Mitsuya KINOSHITA  Fukashi MORISHITA  Teruhiko AMANO  Masaru HARAGUCHI  Makoto HATAKENAKA  Atsushi AMO  Atsushi HACHISUKA  Kazutami ARIMOTO  Hideyuki OZAKI  
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pp.3001-3008  PAPER-Power Optimization
Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks
Satoshi KOMATSU  Masahiro FUJITA  
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pp.3009-3019  PAPER-IP Design
Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms
Jun SAKIYAMA  Naofumi HOMMA  Takafumi AOKI  Tatsuo HIGUCHI  
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pp.3020-3027  PAPER-IP Design
Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers
Hiroyuki OCHI  Tatsuya SUZUKI  Sayaka MATSUNAGA  Yoichi KAWANO  Takao TSUDA  
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pp.3028-3037  PAPER-IP Design
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design
Nattha SRETASEREEKUL  Hiroshi SAITO  Euiseok KIM  Metehan OZCAN  Masashi IMAI  Hiroshi NAKAMURA  Takashi NANYA  
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pp.3038-3048  PAPER-Timing Verification and Test Generation
Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation
Jing-Jia LIOU  Li-C. WANG  Angela KRSTIĆ  Kwang-Ting (Tim) CHENG  
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pp.3049-3055  PAPER-Timing Verification and Test Generation
DFT Timing Design Methodology for Logic BIST
Yasuo SATO  Motoyuki SATO  Koki TSUTSUMIDA  Kazumi HATAYAMA  Kazuyuki NOMOTO  
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pp.3056-3062  PAPER-Timing Verification and Test Generation
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Youhua SHI  Zhe ZHANG  Shinji KIMURA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3063-3071  PAPER-Timing Verification and Test Generation
Seed Selection Procedure for LFSR-Based Random Pattern Generators
Kenichi ICHINO  Ko-ichi WATANABE  Masayuki ARAI  Satoshi FUKUMOTO  Kazuhiko IWASAKI  
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pp.3072-3078  PAPER-Timing Verification and Test Generation
A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
Hideyuki ICHIHARA  Tomoo INOUE  
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pp.3079-3088  PAPER-Simulation Accelerator
Implementation of Java Accelerator for High-Performance Embedded Systems
Motoki KIMURA  Morgan Hirosuke MIKI  Takao ONOYE  Isao SHIRAKAWA  
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pp.3089-3098  PAPER-Simulation Accelerator
Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture
Jun Kyoung KIM  Ho Young KIM  Tag Gon KIM  
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pp.3099-3109  PAPER-Simulation Accelerator
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
Nozomu TOGAWA  Kyosuke KASAHARA  Yuichiro MIYAOKA  Jinku CHOI  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3110-3118  PAPER-Analog Design
Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits
Sheldon X.-D. TAN  C.-J. Richard SHI  
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pp.3119-3126  PAPER-Analog Design
A Fully Independently Adjustable, Integrable Simple Current Controlled Oscillator and Derivative PWM Signal Generator
Montree SIRIPRUCHYANUN  Paramote WARDKEIN  
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pp.3127-3135  PAPER-Analog Design
Red-Black Interval Trees in Device-Level Analog Placement
Sarat C. MARUVADA  Karthik KRISHNAMOORTHY  Florin BALASA  Lucian M. IONESCU  
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pp.3136-3147  PAPER-Place and Routing
VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing
Sheqin DONG  Xianlong HONG  Song CHEN  Xin QI  Ruijie WANG  Jun GU  
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pp.3148-3157  PAPER-Place and Routing
An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair
Kazuya WAKATA  Hiroaki SAITO  Kunihiro FUJIYOSHI  Keishi SAKANUSHI  Takayuki OBATA  Chikaaki KODAMA  
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pp.3158-3167  PAPER-Place and Routing
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design
Jingyu XU  Xianlong HONG  Tong JING  Yici CAI  Jun GU  
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pp.3168-3175  PAPER-Logic and High Level Synthesis
Compact Representations of Logic Functions Using Heterogeneous MDDs
Shinobu NAGAYAMA  Tsutomu SASAO  
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pp.3176-3183  PAPER-Logic and High Level Synthesis
Multi-Cycle Path Detection for Sequential Circuits and Its Application to Real Designs
Hiroyuki HIGUCHI  
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pp.3184-3191  PAPER-Logic and High Level Synthesis
Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
Nobuhiro DOI  Takashi HORIYAMA  Masaki NAKANISHI  Shinji KIMURA  Katsumasa WATANABE  
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pp.3192-3199  PAPER-Logic and High Level Synthesis
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams
Thanyapat SAKUNKONCHAK  Satoshi KOMATSU  Masahiro FUJITA  
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pp.3200-3203  LETTER-Power Optimization
Leakage Power Reduction for Battery-Operated Portable Systems
Yun CAO  Hiroto YASUURA  
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pp.3204-3207  LETTER-IP Design
Experimental Study on Cell-Base High-Performance Datapath Design
Masanori HASHIMOTO  Yoshiteru HAYASHI  Hidetoshi ONODERA  
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pp.3208-3210  LETTER-Timing Verification and Test Generation
Evaluation of Delay Testing Based on Path Selection
Masayasu FUKUNAGA  Seiji KAJIHARA  Sadami TAKEOKA  Shinichi YOSHIMURA  
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pp.3211-3213  LETTER-Analog Design
Design of High-Performance Charge-Pump Circuit for PLL Applications
Chun-Lung HSU  Wu-Hung LU  
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pp.3214-3217  LETTER-Design Methodology
Application of Error Diagnosis Technique to Incremental Synthesis
Hiroshi INOUE  Takahiro IWASAKI  Toshifumi SUGANE  Masahiro NUMA  Keisuke YAMAMOTO  
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pp.3218-3224  LETTER-Design Methodology
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions
Nozomu TOGAWA  Koichi TACHIKAKE  Yuichiro MIYAOKA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3225-3229  LETTER-Design Methodology
Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser
Naohiko SHIMIZU  
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Regular Section

pp.3230-3239  PAPER-Analog Signal Processing
3.3 V 35 mW Second-Order Three-Bit Quadrature Band-Pass ΔΣ Modulator for Digital Radio
Hack-Soo OH  Chang-Gene WOO  Pyung CHOI  Geunbae LIM  Jang-Kyoo SHIN  Jong-Hyun LEE  
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pp.3240-3250  PAPER-Systems and Control
Computation of the Peak of Time Response in the Form of Formal Power Series
Takuya KITAMOTO  
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pp.3251-3258  PAPER-Graphs and Networks
Approximability of the Minimum Maximal Matching Problem in Planar Graphs
Hiroshi NAGAMOCHI  Yukihiro NISHIDA  Toshihide IBARAKI  
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pp.3259-3266  PAPER-Information Security
Constructing c-Secure CRT Codes Using Polynomials over Finite Fields
Mira KIM  Junji SHIKATA  Hirofumi MURATANI  Hideki IMAI  
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pp.3267-3275  PAPER-Image
Video Watermarking of Which Embedded Information Depends on the Distance between Two Signal Positions
Minoru KURIBAYASHI  Hatsukazu TANAKA  
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pp.3276-3282  PAPER-General Fundamentals and Boundaries
A Log-Normal Distribution Model for Electron Multiplying Detector Signals in Charged Particle Beam Equipments
Mitsuru YAMADA  Akinori NISHIHARA  
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pp.3283-3287  LETTER-Engineering Acoustics
Measurement of Early Reflections in a Room with Five Microphone System
Chulmin CHOI  Lae-Hoon KIM  Yangki OH  Sejin DOO  Koeng-Mo SUNG  
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pp.3288-3290  LETTER-Speech and Hearing
Performance Comparison of Single and Multi-Stage Algebraic Codebooks
Sung-Kyo JUNG  Hong-Goo KANG  Dae-Hee YOUN  
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pp.3291-3293  LETTER-Digital Signal Processing
Constrained Location Algorithm Using TDOA Measurements
Hing Cheung SO  Shun Ping HUI  
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pp.3294-3296  LETTER-Analog Signal Processing
Wide-Input Range Variable Resistor Circuit Using an FG-MOSFET
Muneo KUSHIMA  Koichi TANNO  Okihiko ISHIZUKA  
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pp.3297-3302  LETTER-VLSI Design Technology and CAD
An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design
Yeong-Geol KIM  Tag-Gon KIM  
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pp.3303-3305  LETTER-Information Security
A Robust Audio Watermarking Scheme Using Wavelet Modulation
Bing JI  Fei YAN  De ZHANG  
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pp.3306-3309  LETTER-Information Theory
A Call-by-Need Recursive Algorithm for the LogMAP Decoding of a Binary Linear Block Code
Toshiyuki ISHIDA  Yuichi KAJI  
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pp.3310-3313  LETTER-Communication Theory and Signals
OFDM-CDMA with Low PAPR Using Cyclic-Shifted Sequence Mapping
Young-Hwan YOU  Won-Gi JEON  Jeong-Wook SEO  Byoung-Chul SONG  Hyeok-Koo JUNG  
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pp.3314-3317  LETTER-Neural Networks and Bioengineering
A Basic A/D Converter with Trapping Window
Toshimichi SAITO  Hiroshi IMAMURA  Masaaki NAKA  
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