IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

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Volume E85-A No.12  (Publication Date:2002/12/01)
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Special Section on VLSI Design and CAD Algorithms

pp.2567-2567  FOREWORD
FOREWORD
Takashi MITSUHASHI  Toshiro AKINO  
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pp.2568-2576  PAPER-Design Methodology
Quality-Driven Design for Video Applications
Yun CAO  Hiroto YASUURA  
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pp.2577-2585  PAPER-Design Methodology
Design of Asynchronous Controllers with Delay Insensitive Interface
Hiroshi SAITO  Alex KONDRATYEV  Jordi CORTADELLA  Luciano LAVAGNO  Alex YAKOVLEV  Takashi NANYA  
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pp.2586-2595  PAPER-Hardware/Software Codesign
A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors
Shinsuke KOBAYASHI  Kentaro MITA  Yoshinori TAKEUCHI  Masaharu IMAI  
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pp.2596-2602  PAPER-VLSI Design
A Semi-Synchronous Circuit Design Method by Clock Tree Modification
Seiichiro ISHIJIMA  Tetsuaki UTSUMI  Tomohiro OTO  Atsushi TAKAHASHI  
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pp.2603-2611  PAPER-VLSI Design
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation
Jinku CHOI  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.2612-2623  PAPER-VLSI Design
Random Number Generators Implemented with Neighborhood-of-Four, Non-locally Connected Cellular Automata
Barry SHACKLEFORD  Motoo TANAKA  Richard J. CARTER  Greg SNIDER  
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pp.2624-2635  PAPER-VLSI Design
Design Exploration of an Industrial Embedded Microcontroller: Performance, Cost and Software Compatibility
Ing-Jer HUANG  Li-Rong WANG  Yu-Min WANG  Tai-An LU  
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pp.2636-2644  PAPER-Performance Estimation
Performance Estimation at Architecture Level for Embedded Systems
Hiroshi MIZUNO  Hiroyuki KOBAYASHI  Takao ONOYE  Isao SHIRAKAWA  
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pp.2645-2654  PAPER-High Level Synthesis
An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C
Chang-Jae PARK  Ando KI  In-Cheol PARK  Chong-Min KYUNG  
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pp.2655-2666  PAPER-High Level Synthesis
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation
Shinichi NODA  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.2667-2673  PAPER-Optimization of Power and Timing
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications
Kimiyoshi USAMI  Naoyuki KAWABE  Masayuki KOIZUMI  Katsuhiro SETA  Toshiyuki FURUSAWA  
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pp.2674-2683  PAPER-Test Generation
High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph
Eunjung OH  Soo-Hyun KIM  Dong-Ik LEE  Ho-Yong CHOI  
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pp.2684-2692  PAPER-Logic Synthesis
Modular Synthesis of Timed Circuits Using Partial Order Reduction
Tomohiro YONEDA  Eric MERCER  Chris MYERS  
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pp.2693-2700  PAPER-Logic Synthesis
Bi-Partition of Shared Binary Decision Diagrams
Munehiro MATSUURA  Tsutomu SASAO  Jon T. BUTLER  Yukihiro IGUCHI  
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pp.2701-2707  PAPER-Logic Synthesis
Look Up Table Compaction Based on Folding of Logic Functions
Shinji KIMURA  Atsushi ISHII  Takashi HORIYAMA  Masaki NAKANISHI  Hirotsugu KAJIHARA  Katsumasa WATANABE  
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pp.2708-2714  PAPER-Logic Synthesis
A Faster Algorithm of Minimizing AND-EXOR Expressions
Takashi HIRAYAMA  Yasuaki NISHITANI  Toru SATO  
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pp.2715-2724  PAPER-Logic Synthesis
An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs
Yusuke MATSUNAGA  
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pp.2725-2736  PAPER-Logic Synthesis
Accelerating Logic Rewiring Using Implication Analysis Tree
Chin-Ngai SZE  Wangning LONG  Yu-Liang WU  Jinian BIAN  
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pp.2737-2745  PAPER-Logic Simulation
SP2: A Very Large-Scale Event Driven Logic Simulation Hardware
Hirofumi HAMAMURA  Hiroaki KOMATSU  
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pp.2746-2755  PAPER-Clock Scheduling
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
Keiichi KUROKAWA  Takuya YASUI  Yoichi MATSUMURA  Masahiko TOYONAGA  Atsushi TAKAHASHI  
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pp.2756-2763  PAPER-Clock Scheduling
A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees
Makoto SAITOH  Masaaki AZUMA  Atsushi TAKAHASHI  
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pp.2764-2774  PAPER-Timing Analysis
Characterization and Computation of Steiner Routing Based on Elmore's Delay Model
Satoshi TAYU  Mineo KANEKO  
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pp.2775-2784  PAPER-Physical Design
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Shinya YAMASAKI  Shingo NAKAYA  Shin'ichi WAKABAYASHI  Tetsushi KOIDE  
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pp.2785-2794  PAPER-Physical Design
An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy
Chikaaki KODAMA  Kunihiro FUJIYOSHI  
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pp.2795-2798  LETTER-VLSI Design
Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation
Takahiro KAKIMOTO  Hiroyuki OCHI  Takao TSUDA  
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pp.2799-2802  LETTER-Timing Analysis
Increase in Delay Uncertainty by Performance Optimization
Masanori HASHIMOTO  Hidetoshi ONODERA  
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Special Section on Spread Spectrum Techniques and Applications

pp.2803-2803  FOREWORD
FOREWORD
Takaaki HASEGAWA  
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pp.2804-2812  INVITED PAPER
OFDM/CDMA Technologies for Future Broadband Mobile Communication Systems
Masahiro UMEHIRA  Takatoshi SUGIYAMA  
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pp.2813-2821  PAPER
Design and Implementation of an Uplink Baseband Receiver for Wideband CDMA Communications
Hsi-Pin MA  Steve Hengchen HSU  Tzi-Dar CHIUEH  
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pp.2822-2829  PAPER
Performance Improvement of OFDM System with Consideration on the Characteristics of Power-Line Noise
Kazutoshi SUGIMOTO  Hiraku OKADA  Takaya YAMAZATO  Masaaki KATAYAMA  
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pp.2830-2838  PAPER
A Data Embedding Method Considering the Finite Word-Length for High Quality Images
Masaaki FUJIYOSHI  Takashi TACHIBANA  Hitoshi KIYA  
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pp.2839-2846  PAPER
18 Mbit/s Carrier Frequency Offset-Spread Spectrum (CFO-SS) System Using 2.4 GHz ISM Band
Hiroyasu ISHIKAWA  Naoki FUKE  Keizo SUGIYAMA  Hideyuki SHINONAGA  
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pp.2847-2858  PAPER
Online SNR Estimation for Parallel Combinatorial SS Systems in Nakagami Fading Channels
Ken-ichi TAKIZAWA  Shigenobu SASAKI  Jie ZHOU  Shogo MURAMATSU  Hisakazu KIKUCHI  
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pp.2859-2867  PAPER
A New OFDM Demodulation Method with Variable-Length Effective Symbol and ICI Canceller
Noriyoshi SUZUKI  Hideyuki UEHARA  Mitsuo YOKOYAMA  
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pp.2868-2876  PAPER
Medium Access Control Protocol Based on Estimation of Multimedia Traffic with an Adaptive Algorithm in CDMA Packet Communications
Yasuhiro HIRAYAMA  Hiraku OKADA  Takaya YAMAZATO  Masaaki KATAYAMA  
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pp.2877-2880  LETTER
Estimation of NLOS Propagation-Delay Error Improves Hybrid Mobile Station Location
Wuk KIM  Jang-Gyu LEE  Gyu-In JEE  
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pp.2881-2885  LETTER
A Symbol Synchronizer for Multi-Carrier Spread-Spectrum Systems
Shigetaka GOTO  Akira OGAWA  
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Regular Section

pp.2886-2893  PAPER-Digital Signal Processing
Recursive Least Absolute Error Algorithm: Analysis and Simulations
Shin'ichi KOIKE  
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pp.2894-2900  PAPER-Analog Signal Processing
A CMOS Rail-to-Rail Current Conveyor
Takashi KURASHINA  Satomi OGAWA  Kenzo WATANABE  
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pp.2901-2912  PAPER-VLSI Design Technology and CAD
Novel Techniques for Improving Testability Analysis
Yin-He SU  Ching-Hwa CHENG  Shih-Chieh CHANG  
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pp.2913-2922  PAPER-Graphs and Networks
An Optimal File Transfer on Networks with Plural Original Files
Yoshihiro KANEKO  Shoji SHINODA  
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pp.2923-2932  PAPER-Reliability, Maintainability and Safety Analysis
Cost-Effective Analysis of Software Systems with Periodic Rejuvenation
Hiroaki SUZUKI  Tadashi DOHI  Hiroyuki OKAMURA  
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pp.2933-2938  PAPER-Information Theory
Application of a Word-Based Text Compression Method to Japanese and Chinese Texts
Shigeru YOSHIDA  Takashi MORIHARA  Hironori YAHAGI  Noriko ITANI  
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pp.2939-2942  LETTER-Digital Signal Processing
Differential Constant Modulus Algorithm for Anchored Blind Equalization of AR Channels
Teruyuki MIYAJIMA  
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pp.2943-2945  LETTER-VLSI Design Technology and CAD
A Genetic Algorithm for the Minimization of OPKFDDs
Migyoung JUNG  Gueesang LEE  Sungju PARK  Rolf DRECHSLER  
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pp.2946-2949  LETTER-Algorithms and Data Structures
New 2-Factor Covering Designs for Software Testing
Noritaka KOBAYASHI  Tatsuhiro TSUCHIYA  Tohru KIKUNO  
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