IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

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Volume E83-A No.12  (Publication Date:2000/12/25)
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Special Section on VLSI Design and CAD Algorithms

pp.2399-2399  FOREWORD
FOREWORD
Yukihiro NAKAMURA  Takashi KAMBE  
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pp.2400-2408  PAPER-VLSI Architecture
Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI  Masanao YAMAOKA  Yukifumi KOBAYASHI  Hidetoshi ONODERA  Keikichi TAMARU  
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pp.2409-2416  PAPER-VLSI Architecture
Programmable Dataflow Computing on PCA
Norbert IMLIG  Tsunemichi SHIOZAWA  Ryusuke KONISHI  Kiyoshi OGURI  Kouichi NAGAMI  Hideyuki ITO  Minoru INAMORI  Hiroshi NAKADA  
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pp.2417-2425  PAPER-VLSI Architecture
Dynamic Fast Issue (DFI) Mechanism for Dynamic Scheduled Processors
Abderazek BEN ABDALLAH  Mudar SAREM  Masahiro SOWA  
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pp.2426-2430  PAPER-VLSI Architecture
A New Algorithm for the Configuration of Fast Adder Trees
Alberto PALACIOS-PAWLOVSKY  
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pp.2431-2438  PAPER-VLSI Design Methodology
A New Method for Constructing IP Level Power Model Based on Power Sensitivity
Heng-Liang HUANG  Jiing-Yuan LIN  Wen-Zen SHEN  Jing-Yang JOU  
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pp.2439-2445  PAPER-VLSI Design Methodology
A Practical Method for System-Level Bus Architecture Validation
Kazuyoshi TAKEMURA  Masanobu MIZUNO  Akira MOTOHARA  
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pp.2446-2455  PAPER-VLSI Design Methodology
A Specification Style of Four-Phase Handshaking Asynchronous Controllers and the Optimization of Its Return-to-Zero Phase
Rafael K. MORIZAWA  Takashi NANYA  
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pp.2456-2463  PAPER-Co-design and High-level Synthesis
Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes
Mizuki TAKAHASHI  Nagisa ISHIURA  Akihisa YAMADA  Takashi KAMBE  
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pp.2464-2473  PAPER-Co-design and High-level Synthesis
CAM Processor Synthesis Based on Behavioral Descriptions
Nozomu TOGAWA  Tatsuhiko WAKUI  Tatsuhiko YODEN  Makoto TERAJIMA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.2474-2487  PAPER-Co-design and High-level Synthesis
Multicriteria Codesign Optimization for Embedded Multimedia Communication System
I-Horng JENG  Feipei LAI  
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pp.2488-2497  PAPER-Co-design and High-level Synthesis
Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit
Tae-Suh PARK  Chong-Ho LEE  Duck-Jin CHUNG  
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pp.2498-2504  PAPER-Logic Synthesis
Heuristics to Minimize Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU  Tsutomu SASAO  
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pp.2505-2512  PAPER-Logic Synthesis
An Algorithm for Generating Generic BDDs
Tetsushi KATAYAMA  Hiroyuki OCHI  Takao TSUDA  
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pp.2513-2519  PAPER-Logic Synthesis
Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications
Hiroshi SAWADA  Shigeru YAMASHITA  Akira NAGOYA  
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pp.2520-2527  PAPER-Logic Synthesis
Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure
Qiang ZHU  Yusuke MATSUNAGA  Shinji KIMURA  Katsumasa WATANABE  
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pp.2528-2537  PAPER-Logic Synthesis
Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
Barry SHACKLEFORD  Etsuko OKUSHI  Mitsuhiro YASUDA  Hisao KOIZUMI  Katsuhiko SEO  Hiroto YASUURA  
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pp.2538-2544  PAPER-Logic Synthesis
Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture
Tomonori IZUMI  Ryuji KAN  Yukihiro NAKAMURA  
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pp.2545-2551  PAPER-Performance Optimization
Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs
Hsien-Ho CHUANG  Jing-Yang JOU  C. Bernard SHUNG  
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pp.2552-2557  PAPER-Performance Optimization
Clock Schedule Design for Minimum Realization Cost
Tomoyuki YODA  Atsushi TAKAHASHI  
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pp.2558-2568  PAPER-Performance Optimization
A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
Masanori HASHIMOTO  Hidetoshi ONODERA  
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pp.2569-2576  PAPER-Layout Synthesis
An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints
Jun'ichiro MINAMI  Tetsushi KOIDE  Shin'ichi WAKABAYASHI  
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pp.2577-2583  PAPER-Layout Synthesis
A Cell Synthesis Method for Salicide Process Using Assignment Graph
Kazuhisa OKADA  Takayuki YAMANOUCHI  Takashi KAMBE  
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pp.2584-2591  PAPER-Layout Synthesis
WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement
Shunji SAIKA  Masahiro FUKUI  Masahiko TOYONAGA  Toshiro AKINO  
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pp.2592-2599  PAPER-Simulation
A Method for Linking Process-Level Variability to System Performances
Tomohiro FUJITA  Hidetoshi ONODERA  
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pp.2600-2607  PAPER-Test
Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion
Kazuhiro NAKAMURA  Shinji MARUOKA  Shinji KIMURA  Katsumasa WATANABE  
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pp.2608-2615  PAPER-Test
Testability Analysis of Analog Circuits via Determinant Decision Diagrams
Tao PI  Chuan-Jin Richard SHI  
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pp.2616-2622  PAPER-Analog Circuit Design
High-Speed Wide-Locking Range VCO with Frequency Calibration
Takeo YASUDA  
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pp.2623-2626  LETTER-Analog Circuit Design
A 3.3 V CMOS PLL with a Self-Feedback VCO
Yeon Kug MOON  Kwang Sub YOON  
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pp.2627-2630  LETTER-Analog Circuit Design
Design of a Low Power Consumption Pulse-Shaping 1:4 Interpolation FIR Filter for W-CDMA Applications
Keun-Jang RYOO  Jong-Wha CHONG  
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pp.2631-2632  LETTER-High-level Synthesis
High Level Analysis of Clock Regions in a C++ System Description
Luc RYNDERS  Patrick SCHAUMONT  Serge VERNALDE  Ivo BOLSENS  
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Regular Section

pp.2633-2639  PAPER-Engineering Acoustics
Subjective Assessment of the Desired Echo Return Loss for Subband Acoustic Echo Cancellers
Sumitaka SAKAUCHI  Yoichi HANEDA  Shoji MAKINO  Masashi TANAKA  Yutaka KANEDA  
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pp.2640-2648  PAPER-Digital Signal Processing
A Basic Study of Cough Signal Detection for a Life-Support System
Shoichi TAKEDA  Shuichi KATO  Koki TORIUMI  
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pp.2649-2656  PAPER-Analog Signal Processing
Design and Implementation of a Fourth-Order Quadrature Band-Pass Delta-Sigma Modulator for Low-IF Receivers
Sung-Wook JUNG  Chang-Gene WOO  Sang-Won OH  Hae-Moon SEO  Pyung CHOI  
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pp.2657-2663  PAPER-VLSI Design Technology and CAD
Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture
Chung-Hsin LIU  Nen-Fu HUANG  Chiou-Yng LEE  
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pp.2664-2671  PAPER-Numerical Analysis and Optimization
Numerical Calculation of Cylindrical Functions of Complex Order Using Debye's Asymptotic Series
Mohd Abdur RASHID  Masao KODAMA  
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pp.2672-2678  PAPER-Algorithms and Data Structures
An Algorithm for Finding Two Edge-Disjoint Paths in Tournaments
Shin-ichi NAKAYAMA  Shigeru MASUYAMA  
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pp.2679-2688  PAPER-Information Security
Simple and Secure Coin (SAS-Coin)--A Practical Micropayment System
Manjula SANDIRIGAMA  Akihiro SHIMIZU  Matu-Tarow NODA  
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pp.2689-2698  PAPER-Information Theory
Improving the Speed of LZ77 Compression by Hashing and Suffix Sorting
Kunihiko SADAKANE  Hiroshi IMAI  
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pp.2699-2705  PAPER-Coding Theory
Systematic Binary Deletion/Insertion Error Correcting Codes Capable of Correcting Random Bit Errors
Kiattichai SAOWAPA  Haruhiko KANEKO  Eiji FUJIWARA  
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pp.2706-2714  PAPER-Coding Theory
Trellis, Multilevel, and Turbo Codes with DC-Free Characteristic
Chang Ki JEONG  Eon Kyeong JOO  
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pp.2715-2722  PAPER-Neural Networks and Bioengineering
Natural Gradient Learning for Spatio-Temporal Decorrelation: Recurrent Network
Seungjin CHOI  Shunichi AMARI  Andrzej CICHOCKI  
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pp.2723-2735  PAPER-General Fundamentals and Boundaries
Computational Complexity of Finding Highly Co-occurrent Itemsets in Market Basket Databases
Yeon-Dae KWON  Yasunori ISHIHARA  Shougo SHIMIZU  Minoru ITO  
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pp.2736-2738  LETTER-Digital Signal Processing
New Efficient Designs of Discrete and Differentiating FIR Hilbert Transformers
Ishtiaq Rasool KHAN  Ryoji OHBA  
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pp.2739-2742  LETTER-Digital Signal Processing
Convergence Property of Tri-Quantized-x NLMS Algorithm
Kensaku FUJII  Yoshinori TANAKA  
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pp.2743-2746  LETTER-Digital Signal Processing
Generalization of the Cyclic Convolution and Its Fast Computational Systems
Hideo MURAKAMI  
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pp.2747-2750  LETTER-Digital Signal Processing
Improved Fundamental Frequency Estimation Using Parametric Cubic Convolution
Hee-Suk PANG  SeongJoon BAEK  Koeng-Mo SUNG  
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pp.2751-2755  LETTER-Systems and Control
On Input-State Linearization of Nonlinear Systems with Uncertainty
Ho-Lim CHOI  Jong-Tae LIM  
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pp.2756-2757  LETTER-Circuit Theory
An Accurate Offset- and Gain-Compensated Sample/Hold Circuit
Xiaojing SHI  Hiroki MATSUMOTO  Kenji MURAO  
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pp.2758-2761  LETTER-Numerical Analysis and Optimization
Finding All Solutions of Weakly Nonlinear Equations Using Linear Programming
Kiyotaka YAMAMURA  Yoshii HATA  
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pp.2762-2765  LETTER-Information Security
A Practical (t,n) Multi-Secret Sharing Scheme
Hung-Yu CHIEN  Jinn-Ke JAN  Yuh-Min TSENG  
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pp.2766-2769  LETTER-Information Security
Remarks on the Unknown Key Share Attacks
Joonsang BAEK  Kwangjo KIM  
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pp.2770-2774  LETTER-Neural Networks and Bioengineering
Competitive Learning Algorithms Founded on Adaptivity and Sensitivity Deletion Methods
Michiharu MAEDA  Hiromi MIYAJIMA  
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