IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

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Volume E77-A No.12  (Publication Date:1994/12/25)
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Special Section on VLSI Design and CAD Algorithms

pp.1987-1987  FOREWORD
FOREWORD
Toshiro AKINO  
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pp.1988-1998  PAPER
High-Level VLSI Design Specification Validation Using Algorithmic Debugging
Jiro NAGANUMA  Takeshi OGURA  Tamio HOSHINO  
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pp.1999-2009  PAPER
Datapath Scheduling for Behavioral Description with Conditional Branches
Akihisa YAMADA  Toshiki YAMAZAKI  Nagisa ISHIURA  Isao SHIRAKAWA  Takashi KAMBE  
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pp.2010-2016  PAPER
A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI  Seiji KAJIHARA  Kozo KINOSHITA  
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pp.2017-2027  PAPER
Analysis of Pulse Responses of Multi-Conductor Transmission Lines by a Partitioning Technique
Yuichi TANJI  Lingge JIANG  Akio USHIDA  
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pp.2028-2038  PAPER
Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA  Masao SATO  Tatsuo OHTSUKI  
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pp.2039-2044  PAPER
A Graph Bisection Algorithm Based on Subgraph Migration
Kazunori ISOMOTO  Yoshiyasu MIMASA  Shin'ichi WAKABAYASHI  Tetsushi KOIDE  Noriyoshi YOSHIDA  
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pp.2045-2052  PAPER
A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement
Masahiko TOYONAGA  Shih-Tsung YANG  Isao SHIRAKAWA  Toshiro AKINO  
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pp.2053-2057  LETTER
A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
Tetsushi KOIDE  Yoshinori KATSURA  Katsumi YAMATANI  Shin'ichi WAKABAYASHI  Noriyoshi YOSHIDA  
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pp.2058-2066  PAPER
A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs
Ikuo HARADA  Yuichiro TAKEI  Hitoshi KITAZAWA  
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pp.2067-2075  PAPER
A Fast Vectorized Maze Routing Algorithm on a Supercomputer
Yoshio MIKI  
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pp.2076-2084  PAPER
A Modified Genetic Channel Router
Akio SAKAMOTO  Xingzhao LIU  Takashi SHIMAMOTO  
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pp.2085-2091  PAPER
A Multi-Layer Channel Router Using Simulated Annealing
Masahiko TOYONAGA  Chie IWASAKI  Yoshiaki SAWADA  Toshiro AKINO  
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Regular Section

pp.2092-2097  PAPER-Nonlinear Phenomena and Analysis
Chaos Synchronization in Discrete-Time Dynamical Systems and Its Applications
Makoto ITOH  Hiroyuki MURAKAMI  
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pp.2098-2105  PAPER-Ultrasonics
Piezoelectric Ceramic Transformer for Power Supply Operating in Thickness Extensional Vibration Mode
Osamu OHNISHI  Yasuhiro SASAKI  Toshiyuki ZAITSU  Hiromi KISHIE  Takeshi INOUE  
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pp.2106-2108  LETTER-Algorithms, Data Structures and Computational Complexity
A Note on a Completely Linearly Nested Context-Free Grammar and Its Generalization
Tetsuo MORITA  
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pp.2109-2111  LETTER-Neural Networks
Power Law Slowdown of the Neural Learning
Hideyuki CÂTEAU  Tatsuhiro NAKAJIMA  Hiroshi NUNOKAWA  Nobuko FUCHIKAMI  
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pp.2112-2115  LETTER-Neural Networks
Neural Networks for Digital Sequential Circuits
Hiroshi NINOMIYA  Hideki ASAI  
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pp.2116-2119  LETTER-Nonlinear Phenomena and Analysis
Control of Chua's Circuit by Switching a Resistor
Keiji KONISHI  Hiroaki KAWABATA  Yoji TAKEDA  
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