Zule XU


Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error
Yasushi FUKUDA Zule XU Takayuki KAWAHARA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-C  No. 12  pp. 1118-1121
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
IoTneural networkRBMDBNsoft error
 Summary | Full Text:PDF(587.5KB)

Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs
Mitsutoshi SUGAWARA Zule XU Akira MATSUZAWA 
Publication:   
Publication Date: 2017/06/01
Vol. E100-C  No. 6  pp. 576-583
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
AD converterDA convertermeasurementslow-ramphistogram methodmoment methodmissing code
 Summary | Full Text:PDF(1.5MB)

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator
Anugerah FIRDAUZI Zule XU Masaya MIYAHARA Akira MATSUZAWA 
Publication:   
Publication Date: 2017/06/01
Vol. E100-C  No. 6  pp. 548-559
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
charge-pumpdelta-sigmaSAR ADCtime-to-digital converter
 Summary | Full Text:PDF(2.3MB)

A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design
Zule XU Takayuki KAWAHARA 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4  pp. 370-372
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
ring oscillatorphase-locked loopbehavioral modeldigital PLL
 Summary | Full Text:PDF(318KB)

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell
Mitsutoshi SUGAWARA Kenji MORI Zule XU Masaya MIYAHARA Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2435-2443
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
analog synthesisRDACslice-based layoutSKILL language
 Summary | Full Text:PDF(2.2MB)

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC
Zule XU Seungjong LEE Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/02/01
Vol. E98-A  No. 2  pp. 476-484
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
ADPLLcharge pumpSAR-ADCsub-picosecond resolutionTDCtime-to-charge conversion
 Summary | Full Text:PDF(1.6MB)

Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers
Jun Gyu LEE Zule XU Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8  pp. 1337-1346
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
phase-locked loopfrequency synthesizerloop designsettling timeprocess variations
 Summary | Full Text:PDF(1.9MB)

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL
Zule XU Jun Gyu LEE Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1065-1068
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
digital delta-sigma modulator (DDSM)fractional-N PLLdither
 Summary | Full Text:PDF(574.2KB)