Yuzo TAKAMATSU


Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3128-3135
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
test generationtransistor defectsstuck-at testsdefect coverage
 Summary | Full Text:PDF(299.6KB)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3506-3513
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulationtest generationstuck-open faultsstuck-at testsdefect coverage
 Summary | Full Text:PDF(283.9KB)

Post-BIST Fault Diagnosis for Multiple Faults
Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 771-775
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
post-BIST fault diagnosismultiple stuck-at faultscombinational circuitspass/fail information
 Summary | Full Text:PDF(88.5KB)

A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
Koji YAMAZAKI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 661-666
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
fault diagnosisopen faultBISTpass/fail information
 Summary | Full Text:PDF(570.7KB)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 690-699
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
transistor shortfault simulationtest generationstuck-at test tool
 Summary | Full Text:PDF(346.3KB)

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 675-682
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
diagnosisfault modelfault locationfault simulationcombinational circuitspass/fail information
 Summary | Full Text:PDF(491.4KB)

On Finding Don't Cares in Test Sequences for Sequential Circuits
Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/11/01
Vol. E89-D  No. 11  pp. 2748-2755
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationdon't care valuesequential circuitstuck-at fault
 Summary | Full Text:PDF(195KB)

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits
Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 530-536
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
LSI testingsequential circuittest generationlow power dissipationstuck-at fault
 Summary | Full Text:PDF(176KB)

An Alternative Test Generation for Path Delay Faults by Using Ni-Detection Test Sets
Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2650-2658
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test generationpath delay faults N-propagation test-pair setcombinational circuits
 Summary | Full Text:PDF(587.1KB)

Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation
Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1515-1525
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
diagnosiscrosstalk faultfault simulationsequential circuit
 Summary | Full Text:PDF(870.8KB)

Design of C-Testable Modified-Booth Multipliers
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10  pp. 1868-1878
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
multipliermodified Booth Algorithmdesign for testability (DFT)C-testable design
 Summary | Full Text:PDF(873.5KB)

Diagnosing Delay Faults in Combinational Circuits Under the Ambiguous Delay Model
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12  pp. 1563-1571
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitambiguous delay modelmultiple fault diagnosispath-tracing method
 Summary | Full Text:PDF(659.1KB)

A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/11/25
Vol. E82-D  No. 11  pp. 1466-1473
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitmarginal chipgate delay faulttest generationtest with linearity property
 Summary | Full Text:PDF(598KB)

Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 706-715
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
combinational circuitfault diagnosismultiple delay faultdiagnostic rulespath-tracing methodtest-pairs for marginal delays
 Summary | Full Text:PDF(814.1KB)

FOREWORD
Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 643-644
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(94.4KB)

A Method of Multiple Fault Diagnosis in Sequential Circuits by Sensitizing Sequence Pairs
Nobuhiro YANAGIDA Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 28-37
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Testing/Checking
Keyword: 
sequential circuitscircuit level diagnosissensitizing sequence pairsdeduction algorithmsuspected/candidate faults
 Summary | Full Text:PDF(760.6KB)

A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects
Xiangqiu YU Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 822-829
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generationcombinational circuitsredundant faultsdelay effectextended seven-valued calculus
 Summary | Full Text:PDF(657.2KB)

Improved Forward Test Generation of Sequential Circuits Using Variable-Length Time Frames
Yuzo TAKAMATSU Taijiro OGAWA Hiroshi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 832-836
Type of Manuscript:  Special Section LETTER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
forward test generationsequential circuitsvariable-length time framesstate escaping
 Summary | Full Text:PDF(333.1KB)

A Method of Generating Tests for Combinational Circuits with Multiple Faults
Hiroshi TAKAHASHI Nobukage IUCHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/07/25
Vol. E75-D  No. 4  pp. 569-576
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple faultscombinational circuitstest generationrobust tests
 Summary | Full Text:PDF(641KB)

Bit-Serial Squarer in Finite Fields with Characteristic 2
Masakatu MORII Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/08/25
Vol. E73-E  No. 8  pp. 1314-1318
Type of Manuscript:  LETTER
Category: Information Theory and Coding Theory
Keyword: 
 Summary | Full Text:PDF(238.8KB)