Yuichiro MURACHI

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
Yuichiro MURACHI  Yuki FUKUYAMA  Ryo YAMAMOTO  Junichi MIYAKOSHI  Hiroshi KAWAGUCHI  Hajime ISHIHARA  Masayuki MIYAMA  Yoshio MATSUDA  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 457-464
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
optical flow,  real-time video recognition,  VLSI processor, 
  Summary |  Full Text:PDF
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Yuichiro MURACHI  Junichi MIYAKOSHI  Masaki HAMAMOTO  Takahiro IINUMA  Tomokazu ISHIHARA  Fang YIN  Jangchung LEE  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 465-478
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
low power,  motion estimation,  H.264,  systolic array,  MBAFF,  SRAM, 
  Summary |  Full Text:PDF
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture
Junichi MIYAKOSHI  Yuichiro MURACHI  Tetsuro MATSUNO  Masaki HAMAMOTO  Takahiro IINUMA  Tomokazu ISHIHARA  Hiroshi KAWAGUCHI  Masayuki MIYAMA  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3623-3633
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low power,  motion estimation,  H.264,  SIMD,  systolic array, 
  Summary |  Full Text:PDF
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
Junichi MIYAKOSHI  Yuichiro MURACHI  Tomokazu ISHIHARA  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1629-1636
Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
SRAM,  low power,  parallel processing,  image signal processing,  H.264,  MPEG, 
  Summary |  Full Text:PDF
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application
Yuichiro MURACHI  Koji HAMANO  Tetsuro MATSUNO  Junichi MIYAKOSHI  Masayuki MIYAMA  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3492-3499
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low power,  motion estimation,  MPEG2,  HDTV,  IP, 
  Summary |  Full Text:PDF
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation
Junichi MIYAKOSHI  Yuichiro MURACHI  Koji HAMANO  Tetsuro MATSUNO  Masayuki MIYAMA  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 559-569
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
motion estimation,  MPEG,  H.264,  block-matching, 
  Summary |  Full Text:PDF