Yuichi NAKAMURA


Novel Method to Watermark Anonymized Data for Data Publishing
Yuichi NAKAMURA Yoshimichi NAKATSUKA Hiroaki NISHI 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1671-1679
Type of Manuscript:  Special Section PAPER (Special Section on Information and Communication System Security)
Category: Privacy
Keyword: 
anonymizationdistortion attackturbo codewatermarking
 Summary | Full Text:PDF(1.1MB)

A Loitering Discovery System Using Efficient Similarity Search Based on Similarity Hierarchy
Jianquan LIU Shoji NISHIMURA Takuya ARAKI Yuichi NAKAMURA 
Publication:   
Publication Date: 2017/02/01
Vol. E100-A  No. 2  pp. 367-375
Type of Manuscript:  INVITED PAPER (Special Section on Mathematical Systems Science and its Applications)
Category: 
Keyword: 
similarity searchloitering discoveryindexingvideo surveillancemultimedia database
 Summary | Full Text:PDF(2.8MB)

Learning State Recognition in Self-Paced E-Learning
Siyang YU Kazuaki KONDO Yuichi NAKAMURA Takayuki NAKAJIMA Masatake DANTSUJI 
Publication:   
Publication Date: 2017/02/01
Vol. E100-D  No. 2  pp. 340-349
Type of Manuscript:  PAPER
Category: Educational Technology
Keyword: 
e-learning support systemlearning states recognitioninter-personal differencesclassifier selection
 Summary | Full Text:PDF(1.2MB)

Rule-Based Sensor Data Aggregation System for M2M Gateways
Yuichi NAKAMURA Akira MORIGUCHI Masanori IRIE Taizo KINOSHITA Toshihiro YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2943-2955
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Sensor network
Keyword: 
M2M gatewaysensor data aggregationin memory processingIoT (the Internet of Things)
 Summary | Full Text:PDF(784.8KB)

Time Synchronization Technique Using EPON for Next-Generation Power Grids
Yuichi NAKAMURA Andy HARVATH Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2016/04/01
Vol. E99-B  No. 4  pp. 859-866
Type of Manuscript:  Special Section PAPER (Special Section on Autonomous Decentralized Systems Technologies and Applications for Next-Generation Social Infrastructure)
Category: 
Keyword: 
power gridsmart gridtime synchronizationEthernet Passive Optical Network
 Summary | Full Text:PDF(2.6MB)

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies
Masato INAGI Yuichi NAKAMURA Yasuhiro TAKASHIMA Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2572-2583
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
inter-FPGA routingmulti-FPGA systemprototypingtime-multiplexed I/O
 Summary | Full Text:PDF(1.5MB)

Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis
Naoya OKADA Yuichi NAKAMURA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1264-1272
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
write control methodnonvolatile flip-flopstate transition analysisclock gating
 Summary | Full Text:PDF(1.7MB)

A Verification and Analysis Tool Set for Embedded System Design
Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2788-2793
Type of Manuscript:  INVITED PAPER (Special Section on Mathematical Systems Science and its Applications)
Category: 
Keyword: 
embedded systemsverification
 Summary | Full Text:PDF(1.7MB)

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3539-3547
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
FPGA prototypingILPI/O pins constraintverificationtime-multiplexed I/O
 Summary | Full Text:PDF(309.4KB)

Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
Lei CHEN Takashi HORIYAMA Yuichi NAKAMURA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3531-3538
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
power gatingmulti-threshold CMOS (MTCMOS) technologyBDDcontrolling valueleakage power reduction
 Summary | Full Text:PDF(767KB)

Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
Yuko HASHIZUME Yasuhiro TAKASHIMA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/09/01
Vol. E91-A  No. 9  pp. 2322-2327
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
post-silicon clock-timing tuningdeskewprogrammable delay element (PDE)linear programmingtotally unimodular
 Summary | Full Text:PDF(574.5KB)

Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
Kohei HOSOKAWA Katsunori TANAKA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2810-2817
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
FPGA-based hardware emulatorsSDRAMmemory controllerclock generator
 Summary | Full Text:PDF(907.9KB)

A Relocation Method for Circuit Modifications
Kunihiko YANAGIBASHI Yasuhiro TAKASHIMA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2743-2751
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
non full-reverse-order constraintcircuit modificationrelocationsequence-pairsimulated annealing
 Summary | Full Text:PDF(613.9KB)

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5  pp. 924-931
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
circuit partitioningtime-multiplexed I/OFPGApin constraint
 Summary | Full Text:PDF(401.7KB)

Fast FPGA-Emulation-Based Simulation Environment for Custom Processors
Yuichi NAKAMURA Kouhei HOSOKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3464-3470
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
custom processorsimulationemulationFPGA
 Summary | Full Text:PDF(1.5MB)

Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs
Yuichi NAKAMURA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3458-3463
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
SoCpower consumptionpower estimationtoggle rate
 Summary | Full Text:PDF(724.2KB)

An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs
Yuichi NAKAMURA Ko YOSHIKAWA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3351-3357
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic designengineering change orderspartitioning
 Summary | Full Text:PDF(658.2KB)

Timing Optimization Methodology Based on Replacing Flip-Flops by Latches
Ko YOSHIKAWA Keisuke KANAMARU Yasuhiko HAGIHARA Shigeto INUI Yuichi NAKAMURA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3151-3158
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesissequential circuittiming optimizationlevel-sensitive latchformal verification
 Summary | Full Text:PDF(402.1KB)