Young-Chan JANG


A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display
Ho-Seong KIM Pil-Ho LEE Jin-Wook HAN Seung-Hun SHIN Seung-Wuk BAEK Doo-Ill PARK Yongkyu SEO Young-Chan JANG 
Publication:   
Publication Date: 2017/11/01
Vol. E100-C  No. 11  pp. 1035-1038
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
transmitter bridge chipMIPI D-PHYDSIFPGA-based frame generatorphase-locked loop
 Summary | Full Text:PDF(616.5KB)

A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators
Sang-Min PARK Yeon-Ho JEONG Yu-Jeong HWANG Pil-Ho LEE Yeong-Woong KIM Jisu SON Han-Yeol LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 651-654
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
asynchronous successive approximation registeranalog-to-digital convertermeta-stability detectorreplica comparator
 Summary | Full Text:PDF(1.2MB)

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis
Pil-Ho LEE Yu-Jeong HWANG Han-Yeol LEE Hyun-Bae LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/04/01
Vol. E99-C  No. 4  pp. 440-443
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
on-chip monitoring circuitchip-to-chip interfaceanalog-to-digital converterphase-locked loop-based frequency synthesizersub-sampling
 Summary | Full Text:PDF(937.6KB)

A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces
Kwang-Hun LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/08/01
Vol. E97-C  No. 8  pp. 837-840
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
scalable low voltage signalingtransmitterimpedance calibrationcommon mode voltage
 Summary | Full Text:PDF(3.6MB)

A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications
Mungyu KIM Hoon-Ju CHUNG Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6  pp. 519-525
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
digital-to-analog converterresistor stringlogarithmic time interpolatorlow-pass filterdecoder
 Summary | Full Text:PDF(1.6MB)

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle
Pil-Ho LEE Hyun Bae LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/05/01
Vol. E97-C  No. 5  pp. 463-467
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
multi-phase DLLharmonic lockcoarse-locking circuitinitial phase detectorduty cycle
 Summary | Full Text:PDF(1.3MB)

An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 88 Point EEG/MEG Acquisition System
Ji-Hun EO Yeon-Ho JEONG Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/02/01
Vol. E96-A  No. 2  pp. 453-458
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
successive approximationanalog-to-digital convertertime-domain comparatordaisy channel
 Summary | Full Text:PDF(1.2MB)

Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk
Hyun Bae LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/06/01
Vol. E95-C  No. 6  pp. 1086-1088
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
far-end crosstalkmirrored serpentine microstrip linehigh-speed digital signalingtime domain reflectometry
 Summary | Full Text:PDF(730.6KB)

A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface
Ji-Hun EO Sang-Hun KIM Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/11/01
Vol. E94-C  No. 11  pp. 1798-1801
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
successive approximationanalog-to-digital convertersplit-capacitor-based digital-to-analog convertertime-domain comparator
 Summary | Full Text:PDF(698.3KB)

A Bootstrapped Analog Switch with Constant On-Resistance
Sang-hun KIM Yong-Hwan LEE Hoon-Ju CHUNG Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1069-1071
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
bootstrapped analog switchinput-sampling switchanalog-to-digital converteron-resistance
 Summary | Full Text:PDF(245.1KB)

A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface
Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2  pp. 633-638
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
phase adjusterphase skewsource synchronous double data rate signalingtime-domain reflectometry
 Summary | Full Text:PDF(2.1MB)

A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination
Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6  pp. 861-863
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
transmittersource terminationoutput impedancesingle-ended signalingdiagnostic modeswing level control
 Summary | Full Text:PDF(1.6MB) | (Errata[Uploaded on July 1,2010])

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator
Young-Chan JANG Jun-Hyun BAE Sang-Hune PARK Jae-Yoon SIM Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6  pp. 1156-1164
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
flash ADCtime-interleavingphase-locked-loopdigital phase adjusterdigital duty cycle corrector
 Summary | Full Text:PDF(1.5MB)

An 8-GS/s 4-Bit 340 mW CMOS Time Interleaved Flash Analog-to-Digital Converter
Young-Chan JANG Sang-Hune PARK Seung-Chan HEO Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/02/01
Vol. E87-A  No. 2  pp. 350-356
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog-to-digital convertertime interleaved flash converterresistor averagingdistributed track-and-holdphase locked loop
 Summary | Full Text:PDF(595.3KB)

An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter
Seung-Chan HEO Young-Chan JANG Sang-Hune PARK Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 676-681
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
analog-to-digital converter (ADC)resistor averagingfoldinginterpolatingdifferential logic
 Summary | Full Text:PDF(895.1KB)