IEICE SEARCH SYSTEM

Youji IDEI

Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOSSRAM Kenichi OHHATA Takeshi KUSUNOKI Hiroaki NAMBU Kazuo KANETANI Toru MASUDA Masayuki OHAYASHI Satomi HAMAMOTO Kunihiko YAMAGUCHI Youji IDEI Noriyuki HOMMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/03/20 Vol. E79-C No. 3 pp. 415-423 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: redundancy, ECL-CMOS SRAM, SRAM with logic gate, BiCMOS,
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A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM Hiroaki NAMBU Kazuo KANETANI Youji IDEI Toru MASUDA Keiichi HIGETA Masayuki OHAYASHI Masami USAMI Kunihiko YAMAGUCHI Toshiyuki KIKUCHI Takahide IKEDA Kenichi OHHATA Takeshi KUSUNOKI Noriyuki HOMMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/20 Vol. E78-C No. 6 pp. 739-747 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
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Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time Kenichi OHHATA Yoshiaki SAKURAI Hiroaki NAMBU Kazuo KANETANI Youji IDEI Toshirou HIRAMOTO Nobuo TAMBA Kunihiko YAMAGUCHI Masanori ODAKA Kunihiko WATANABE Takahide IKEDA Noriyuki HOMMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/20 Vol. E76-C No. 11 pp. 1611-1619 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: SRAM Keyword: ECL-CMOS SRAM, 64-kb, noise reduction, crosstalk,
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Redundancy Technique for Ultra-High-Speed Static RAMs Hiroaki NAMBU Kazuo KANETANI Youji IDEI Kunihiko YAMAGUCHI Toshirou HIRAMOTO Nobuo TAMBA Kunihiko WATANABE Masanori ODAKA Takahide IKEDA Kenichi OHHATA Yoshiaki SAKURAI Noriyuki HOMMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/04/20 Vol. E76-C No. 4 pp. 641-648 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: redundancy technique, static RAM (SRAM), focused ion beam (FIB), laser chemical vapor deposition (L-CVD), access time,
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Soft-Error Immune 180-µm² SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs Youji IDEI Takeo SHIBA Noriyuki HOMMA Kunihiko YAMAGUCHI Tohru NAKAMURA Takahiro ONAI Youichi TAMAKI Yoshiaki SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/20 Vol. E75-C No. 11 pp. 1369-1376 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Keyword: soft error, SICOS, bipolar RAM, 256 Kbit,
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High-Speed Sensing Techniques for Ultrahigh-Speed SRAM's Hiroaki NAMBU Kazuo KANETANI Youji IDEI Noriyuki HOMMA Kunihiko YAMAGUCHI Toshirou HIRAMOTO Nobuo TAMBA Masanori ODAKA Kunihiko WATANABE Takahide IKEDA Kenichi OHHATA Yoshiaki SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/20 Vol. E75-C No. 4 pp. 530-538 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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Alpha-Particle-Induced Charge Amplification by Parasitic npn Transistor in Ultra-High-Speed Bipolar RAMs Hiroaki NAMBU Youji IDEI Kazuo KANETANI Kunihiko YAMAGUCHI Noriyuki HOMMA Kenichi OHHATA Yoshiaki SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/20 Vol. E74-C No. 4 pp. 839-844 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: SRAM Keyword:
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