Youhua SHI


Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs
Ken HAYAMIZU Nozomu TOGAWA Masao YANAGISAWA Youhua SHI 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7  pp. 1014-1024
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
approximate computingenergy-efficientadderGeAr
 Summary | Full Text:PDF(2.7MB)

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element
Saki TAJIMA Nozomu TOGAWA Masao YANAGISAWA Youhua SHI 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7  pp. 1025-1034
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
soft errorlow-powerlatchC-element
 Summary | Full Text:PDF(1.6MB)

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists
Masaru OYA Youhua SHI Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Satoshi GOTO Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2537-2546
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
hardware Trojansgolden-IC freeclassificationidentificationgate-level netlist
 Summary | Full Text:PDF(2.3MB)

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead
Shinnosuke YOSHIDA Youhua SHI Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1406-1418
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
timing-error predictionrobust designdelay variationoverclocking
 Summary | Full Text:PDF(2.5MB)

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design
Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1376-1391
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesisenergy-optimizationinterconnection delaymultiple clock domains
 Summary | Full Text:PDF(2.2MB)

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages
Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2597-2611
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisinterconnection delayenergy-optimizationdynamic multiple supply voltages
 Summary | Full Text:PDF(2.1MB)

Scan-Based Attack on AES through Round Registers and Its Countermeasure
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2338-2346
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
scan-based side channel attackcrypto implementationsecuritytestability
 Summary | Full Text:PDF(2MB)

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3119-3127
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
scan testtest data compressionX-masking
 Summary | Full Text:PDF(851.7KB)

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n)
Kazuyuki TANIMURA Ryuta NARA Shunitsu KOHARA Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2304-2317
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
elliptic curve cryptographydual-radixmodular multiplicationMontgomery multiplicationscalabilityunified
 Summary | Full Text:PDF(1.6MB)

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3514-3523
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
scan testtest data compressionX-masking
 Summary | Full Text:PDF(583.3KB)

A Secure Test Technique for Pipelined Advanced Encryption Standard
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 776-780
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
scan testsecuritytest quality
 Summary | Full Text:PDF(145.8KB)

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains
Youhua SHI Nozomu TOGAWA Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 996-1004
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
test data compressiontest channelsscan test
 Summary | Full Text:PDF(445.2KB)

A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction
Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3208-3215
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test data compressionscan chain reconfigurationrun-length codingscan-in power consumption
 Summary | Full Text:PDF(465.2KB)

A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs
Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3193-3199
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test data compressiontest slicemultiple scan chainATE
 Summary | Full Text:PDF(738.1KB)

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3056-3062
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
reseedingLFSRBISTtest pattern generation
 Summary | Full Text:PDF(1MB)