Yoshinobu HIGAMI


Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems
Tsutomu INAMOTO Yoshinobu HIGAMI Shin-ya KOBAYASHI 
Publication:   
Publication Date: 2017/02/01
Vol. E100-A  No. 2  pp. 385-394
Type of Manuscript:  Special Section PAPER (Special Section on Mathematical Systems Science and its Applications)
Category: 
Keyword: 
elevator operation problemmulti-car elevator systeminteger linear programminginterference prevention
 Summary | Full Text:PDF(1MB)

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6  pp. 1323-1331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationfault simulationclock linedelay fault
 Summary | Full Text:PDF(595KB)

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool
Yoshinobu HIGAMI Satoshi OHNO Hironori YAMAOKA Hiroshi TAKAHASHI Yoshihiro SHIMIZU Takashi AIKYO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/04/01
Vol. E95-D  No. 4  pp. 1093-1100
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
fault diagnosistest generationtransition faultsstuck-at ATPG
 Summary | Full Text:PDF(502.5KB)

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3128-3135
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
test generationtransistor defectsstuck-at testsdefect coverage
 Summary | Full Text:PDF(299.6KB)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3506-3513
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulationtest generationstuck-open faultsstuck-at testsdefect coverage
 Summary | Full Text:PDF(283.9KB)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 690-699
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
transistor shortfault simulationtest generationstuck-at test tool
 Summary | Full Text:PDF(346.3KB)

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 675-682
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
diagnosisfault modelfault locationfault simulationcombinational circuitspass/fail information
 Summary | Full Text:PDF(491.4KB)

Post-BIST Fault Diagnosis for Multiple Faults
Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 771-775
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
post-BIST fault diagnosismultiple stuck-at faultscombinational circuitspass/fail information
 Summary | Full Text:PDF(88.5KB)

On Finding Don't Cares in Test Sequences for Sequential Circuits
Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/11/01
Vol. E89-D  No. 11  pp. 2748-2755
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationdon't care valuesequential circuitstuck-at fault
 Summary | Full Text:PDF(195KB)

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits
Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 530-536
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
LSI testingsequential circuittest generationlow power dissipationstuck-at fault
 Summary | Full Text:PDF(176KB)

Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation
Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1515-1525
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
diagnosiscrosstalk faultfault simulationsequential circuit
 Summary | Full Text:PDF(870.8KB)

Test Generation for Sequential Circuits under IDDQ Testing
Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 689-696
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
sequential circuittest generationIDDQ testingbridging fault
 Summary | Full Text:PDF(707.5KB)

A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2010-2016
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
sequential circuittest generationdesign for testabilityscan circuitreduced scan shift
 Summary | Full Text:PDF(625.9KB)

Test Sequence Generation for Sequential Circuits with Distinguishing Sequences
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1730-1737
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
distinguishing sequencestuck-at faultsequential circuittest sequence generationdesign rechnique
 Summary | Full Text:PDF(696.2KB)