Yoshiki WADA


Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits
Koichiro MASHIKO Kimio UEDA Tsutomu YOSHIMURA Takanori HIROTA Yoshiki WADA Jun TAKASOH Kazuo KUBO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11  pp. 1697-1704
Type of Manuscript:  INVITED PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
silicon on insulator (SOI)complementary metal oxide semiconductor (CMOS)emitter coupled logic (ECL)
 Summary | Full Text:PDF(2.1MB)

A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors
Kimio UEDA Koji NII Yoshiki WADA Shigenobu MAEDA Toshiaki IWAMATSU Yasuo YAMAGUCHI Takashi IPPOSHI Shigeto MAEGAWA Koichiro MASHIKO Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 205-211
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
SOICMOSfield-shield isolationgate arraylow-powerhigh-speed
 Summary | Full Text:PDF(2MB)

SOI/CMOS Circuit Design for High-Speed Communication LSIs
Kimio UEDA Yoshiki WADA Takanori HIROTA Shigenobu MAEDA Koichiro MASHIKO Hisanori HAMANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 886-892
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Structure Devices
Keyword: 
multiplexerdemultiplexerCMOS deviceSOI/CMOS devicelow-powerhigh-speed
 Summary | Full Text:PDF(558.1KB)