Yoshiki SAITO

Leakage Power Reduction of a Dynamically Reconfigurable Processor Using Dual-Vth Cells
Keiichiro HIRAI  Toru SANO  Masaru KATO  Yoshiki SAITO  Hideharu AMANO 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2011/01/01
Vol. J94-D  No. 1  pp. 303-311
Type of Manuscript: PAPER
Category: 
Keyword: 
dynamically reconfigurable processor,  low leakage design,  Dual-Vth, 
  Summary |  Full Text(in Japanese):PDF (676.3KB)
Data Bus Configuration: Configuration Data Transfer Time Reduction Method for Dynamically Reconfigurable Devices
Toru SANO  Masaru KATO  Yoshiki SAITO  Hideharu AMANO 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2010/12/01
Vol. J93-D  No. 12  pp. 2579-2586
Type of Manuscript: PAPER
Category: 
Keyword: 
dynamically reconfigurable processor array,  configuration data transfer time, 
  Summary |  Full Text(in Japanese):PDF (491.6KB)
Power Analysis and Power Reduction Techniques for Dynamically Reconfigurable Processors
Takashi NISHIMURA  Keiichiro HIRAI  Yoshiki SAITO  Takuro NAKAMURA  Satoshi TSUTSUMI  Yohei HASEGAWA  Hideharu AMANO 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2009/10/01
Vol. J92-D  No. 10  pp. 1763-1771
Type of Manuscript: PAPER
Category: 
Keyword: 
dynamically reconfigurable processor,  low power consumption, 
  Summary |  Full Text(in Japanese):PDF (461.3KB)