Yoshikazu YABE


Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM
Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 759-767
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
integration of DRAM and logicembedded DRAMlow powerhigh memory bandwidth
 Summary | Full Text:PDF(951.7KB)

Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model
Takahiro HANYU Yoshikazu YABE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1126-1132
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
resonant-tunneling diode modeluniversal literalload line methodmultiple-valued PLAwired logiccurrent-mode linear summation
 Summary | Full Text:PDF(520.6KB)