Yoshiharu AIMOTO


Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM
Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 759-767
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
integration of DRAM and logicembedded DRAMlow powerhigh memory bandwidth
 Summary | Full Text:PDF(951.7KB)

A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs
Tadahiko SUGIBAYASHI Isao NARITAKE Hiroshi TAKADA Ken INOUE Ichiro YAMAMOTO Tatsuya MATANO Mamoru FUJITA Yoshiharu AIMOTO Toshio TAKESHIMA Satoshi UTSUGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1323-1327
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
memoryDRAMtest
 Summary | Full Text:PDF(588.5KB)