Yoichi ONISHI


SoC Architecture Synthesis Methodology Based on High-Level IPs
Michiaki MURAOKA Hiroaki NISHI Rafael K. MORIZAWA Hideaki YOKOTA Yoichi ONISHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3057-3067
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
system level designarchitecture synthesishigh level IPCAD
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