Yohei NAKATA

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM
Jinwook JUNG  Yohei NAKATA  Shunsuke OKUMURA  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 528-537
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-voltage adaptive cache design,  reconfiguring associativity,  dynamic voltage frequency scaling,  7T/14T SRAM, 
  Summary |  Full Text:PDF
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
Yohei NAKATA  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 523-533
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
network-on-chip,  process variation,  adaptive circuits,  routing algorithm, 
  Summary |  Full Text:PDF
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
Shunsuke OKUMURA  Yuki KAGIYAMA  Yohei NAKATA  Shusuke YOSHIMOTO  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2693-2700
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
SRAM DMA,  transactional memory,  checkpoint and recovery,  multi-core processor, 
  Summary |  Full Text:PDF