Yasutaka HORIBA


An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design
Takayuki GYOHTEN  Fukashi MORISHITA  Isamu HAYASHI  Mako OKAMOTO  Hideyuki NODA  Katsumi DOSAKA  Kazutami ARIMOTO  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1519-1525
Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
PVT variationtemperature detectionseries regulator
  Summary |  Full Text:PDF (1.5MB)

A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Toshiki KANAMOTO  Tetsuya WATANABE  Mitsutoshi SHIROTA  Masayuki TERAI  Tatsuya KUNIKIYO  Kiyoshi ISHIKAWA  Yoshihide AJIOKA  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3463-3470
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
SoCinterconnectphysical parameterlow-kcapacitanceresistancelayout parasitic extraction
  Summary |  Full Text:PDF (593.7KB)

A Programmable Geometry Processor with Enhanced Four-Parallel SIMD Type Processing Core for PC-Based 3D Graphics
Hiroyuki KAWAI  Yoshitsugu INOUE  Junko KOBARA  Robert STREITENBERGER  Hiroaki SUZUKI  Hiroyasu NEGISHI  Masatoshi KAMEYAMA  Kazunari INOUE  Yasutaka HORIBA  Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5  pp. 1200-1210
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
3D graphicsprogrammablegeometrySIMDclip test
  Summary |  Full Text:PDF (1.7MB)

An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core
Hiroshi SEGAWA  Yoshinori MATSUURA  Satoshi KUMAKI  Tetsuya MATSUMURA  Stefan SCOTZNIOVSKY  Shu MURAYAMA  Tetsuro WADA  Ayako HARADA  Eiji OHARA  Ken-ichi ASANO  Toyohiko YOSHIDA  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 202-211
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
video encoderMPEG-2media-processoraudio encodersystem encoderembedded software
  Summary |  Full Text:PDF (1.2MB)

A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores
Tetsuya MATSUMURA  Satoshi KUMAKI  Hiroshi SEGAWA  Kazuya ISHIHARA  Atsuo HANAMI  Yoshinori MATSUURA  Stefan SCOTZNIOVSKY  Hidehiro TAKATA  Akira YAMADA  Shu MURAYAMA  Tetsuro WADA  Hideo OHIRA  Toshiaki SHIMADA  Ken-ichi ASANO  Toyohiko YOSHIDA  Masahiko YOSHIMOTO  Koji TSUCHIHASHI  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/01/01
Vol. E84-C  No. 1  pp. 108-122
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
video encoderMPEG-2media-processoraudio encodersystem encodermotion estimation
  Summary |  Full Text:PDF (2.1MB)

A Sub 1-V L-Band Low Noise Amplifier in SOI CMOS
Hiroshi KOMURASAKI  Hisayasu SATO  Kazuya YAMAMOTO  Kimio UEDA  Shigenobu MAEDA  Yasuo YAMAGUCHI  Nagisa SASAKI  Takahiro MIKI  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/02/20
Vol. E83-A  No. 2  pp. 220-227
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
SOI CMOSlow noise amplifierL bandlow voltageRF
  Summary |  Full Text:PDF (1.7MB)

A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors
Kimio UEDA  Koji NII  Yoshiki WADA  Shigenobu MAEDA  Toshiaki IWAMATSU  Yasuo YAMAGUCHI  Takashi IPPOSHI  Shigeto MAEGAWA  Koichiro MASHIKO  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/20
Vol. E83-C  No. 2  pp. 205-211
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
SOICMOSfield-shield isolationgate arraylow-powerhigh-speed
  Summary |  Full Text:PDF (2MB)

A Design of High-Speed 4-2 Compressor for Fast Multiplier
Hiroshi MAKINO  Hiroaki SUZUKI  Hiroyuki MORINAKA  Yasunobu NAKASE  Hirofumi SHINOHARA  Koichiro MASHIKO  Tadashi SUMI  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/20
Vol. E79-C  No. 4  pp. 538-548
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
4-2 compressormultiplierredundant binarytransmission gateCMOS circuit
  Summary |  Full Text:PDF (1015.1KB)

A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply
Takahiro MIKI  Yasuyuki NAKAMURA  Yoshikazu NISHIKAWA  Keisuke OKADA  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/20
Vol. E76-C  No. 5  pp. 738-745
Type of Manuscript: Special Section PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)
Category: 
Keyword: 
low supply voltageD/A convertervideo systembattery powered system
  Summary |  Full Text:PDF (723.2KB)

Transient Analysis of Switched Current Source
Takahiro MIKI  Yasuyuki NAKAMURA  Keisuke OKADA  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/03/20
Vol. E75-C  No. 3  pp. 288-296
Type of Manuscript: Special Section PAPER (Special Issue on Analog LSI and Related Technology)
Category: 
Keyword: 
current sourcecurrent switchswitched current sourcetransient analysisD/A converterdata converter
  Summary |  Full Text:PDF (760.4KB)

A High-Performance Reconfigurable Line Memory Macrocell for Video Signal Processing ASICs
Tetsuya MATSUMURA  Masahiko YOSHIMOTO  Atsushi MAEDA  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/20
Vol. E74-C  No. 11  pp. 3787-3795
Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Core and Macrocells
Keyword: 
  Summary |  Full Text:PDF (988.1KB)

Influence of Non-Zero Resistance of Analog Ground Line in D/A Converter
Takahiro MIKI  Yasuyuki NAKAMURA  Masao NAKAYA  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/04/20
Vol. E69-E  No. 4  pp. 258-260
Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
Category: Silicon Devices and Integrated Circuits
Keyword: 
  Summary |  Full Text:PDF (172.8KB)