Yasushi KUBOTA


Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays
Sadahiro TANI Yoshihiro UCHIDA Makoto FURUIE Shuji TSUKIYAMA BuYeol LEE Shuji NISHI Yasushi KUBOTA Isao SHIRAKAWA Shigeki IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2923-2932
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
interconnectLCDparasitic capacitancesignal integritycircuit simulation
 Summary | Full Text:PDF(704.6KB)

A Proposal of New Multiple-Valued Mask-ROM Design
Yasushi KUBOTA Shinji TOYOYAMA Yoji KANIE Shuhei TSUCHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4  pp. 601-607
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
semiconductor devicesmask-ROMmultiple-valuethreshold voltagechannel length
 Summary | Full Text:PDF(567.1KB)

4-2 Compressor with Complementary Pass-Transistor Logic
Youji KANIE Yasushi KUBOTA Shinji TOYOYAMA Yasuaki IWASE Shuhei TSUCHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4  pp. 647-649
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
electronic circuitsmultiplierregularly structured Wallace tree4-2 compressorcomplementary pass-transistor logic
 Summary | Full Text:PDF(174.2KB)

Alternately-Activated Open Bitline Technique for High Density DRAMs
Yasushi KUBOTA Yasuaki IWASE Katsuji IGUCHI Junkou TAKAGI Toru WATANABE Keizo SAKIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10  pp. 1259-1266
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
DRAM bitline capacitance noise power
 Summary | Full Text:PDF(733.8KB)