Yasushi KAWAGUCHI


Efficient Routability Checking for Global Wires in Planar Layouts
Naoyuki ISO Yasushi KAWAGUCHI Tomio HIRATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1878-1882
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
layout designroutabilityrouting
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