Yasuo SUGURE


A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme
Go MATSUKAWA Yohei NAKATA Yasuo SUGURE Shigeru OHO Yuta KIMI Masafumi SHIMOZAWA Shuhei YOSHIDA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4  pp. 333-339
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
dual modular redundancycheckpoint recoveryfault-tolerance
 Summary | Full Text:PDF(3.5MB)

Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo SUGURE Seiji TAKEUCHI Yuichi ABE Hiromichi YAMADA Kazuya HIRAYANAGI Akihiko TOMITA Kesami HAGIWARA Takeshi KATAOKA Takanori SHIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6  pp. 844-850
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
microcontrollerRISClow-latencyinterrupt response timesmaller code size
 Summary | Full Text:PDF(1.5MB)