Yasuo SATO


Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair
Gian MAYUGA Yuta YAMATO Tomokazu YONEDA Yasuo SATO Michiko INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/10/01
Vol. E99-D  No. 10  pp. 2591-2599
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
memory repairmemory reliabilityin-field test and repairECCin-field repair strategyremapping
 Summary | Full Text:PDF(2.4MB)

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
Akihiro TOMITA Xiaoqing WEN Yasuo SATO Seiji KAJIHARA Kohei MIYASE Stefan HOLST Patrick GIRARD Mohammad TEHRANIPOOR Laung-Terng WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10  pp. 2706-2718
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
at-speed scan-based logic BISTcapture power safetymaskingIR-droptransition delay faultlong sensitized path
 Summary | Full Text:PDF(3.5MB)

Scan-Out Power Reduction for Logic BIST
Senling WANG Yasuo SATO Seiji KAJIHARA Kohei MIYASE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 2012-2020
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
low powerBISTmulti-cycle testshift power
 Summary | Full Text:PDF(2.2MB)

Post-BIST Fault Diagnosis for Multiple Faults
Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 771-775
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
post-BIST fault diagnosismultiple stuck-at faultscombinational circuitspass/fail information
 Summary | Full Text:PDF(88.5KB)

A Statistical Quality Model for Delay Testing
Yasuo SATO Shuji HAMADA Toshiyuki MAEDA Atsuo TAKATORI Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 349-355
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
Keyword: 
delay testingquality modeldefect distribution
 Summary | Full Text:PDF(933.9KB)

Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs
Kazumi HATAYAMA Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Yasuo SATO Takaharu NAGUMO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3318-3323
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
BISTtest pattern generatorneighborhood patternLFSRreseeding
 Summary | Full Text:PDF(429.3KB)

Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration
Yasuo SATO Iwao YAMAZAKI Hiroki YAMANAKA Toshio IKEDA Masahiro TAKAKURA Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/09/01
Vol. E87-D  No. 9  pp. 2179-2185
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
diagnosisopen faultcoupling effect
 Summary | Full Text:PDF(439.5KB)

DFT Timing Design Methodology for Logic BIST
Yasuo SATO Motoyuki SATO Koki TSUTSUMIDA Kazumi HATAYAMA Kazuyuki NOMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3049-3055
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
DFTat-speed BISTtiming designmultiple-clock
 Summary | Full Text:PDF(635.5KB)

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
delay testingpath selectionfault simulationtest generationpath-status graph
 Summary | Full Text:PDF(322.4KB)