Yasuo OHARA


The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI
Takehiko NAKAO Masanori KUWAHARA Yasuo OHARA Reiji ARIYOSHI Toshihiko KITAZUME Naoki SUGAWA Takeshi OGAWARA Satoshi ODA Shoji NOMURA Yuichi MIYAZAWA Akira KANUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 746-749
Type of Manuscript:  Special Section LETTER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
PLLjitterATMQPLC
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