Yasuo INOUE


Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation
Yasumasa TSUKAMOTO Tatsuya KUNIKIYO Koji NII Hiroshi MAKINO Shuhei IWADE Kiyoshi ISHIKAWA Yasuo INOUE Norihiko KOTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 439-446
Type of Manuscript:  Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
embedded SRAMscaling merit3-dimensional interconnect simulation50 and 70 nm technology nodes
 Summary | Full Text:PDF(982.7KB)

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM
Fukashi MORISHITA Yasuo YAMAGUCHI Takahisa EIMORI Toshiyuki OASHI Kazutami ARIMOTO Yasuo INOUE Tadashi NISHIMURA Michihiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3  pp. 544-552
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword: 
SOI-DRAMfloating bodyhigh speedlow powerdata retention characteristics
 Summary | Full Text:PDF(592.4KB)

Analysis of the Delay Distributions of 0.5 µm SOI LSIs
Toshiaki IWAMATSU Takashi IPPOSHI Yasuo YAMAGUCHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Yasuo INOUE Tadashi HIRAO Tdashi NISHIMURA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3  pp. 464-471
Type of Manuscript:  Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
SOISIMOXdivideradderhigh-speedlow voltage
 Summary | Full Text:PDF(735.3KB)

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's
Yasuo YAMAGUCHI Toshiyuki OASHI Takahisa EIMORI Toshiaki IWAMATSU Shouichi MITAMOTO Katsuhiro SUMA Takahiro TSURUDA Fukashi MORISHITA Masakazu HIROSE Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Yasuo INOUE Tadashi NISHIMURA Hirokazu MIYOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 772-780
Type of Manuscript:  INVITED PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
SOLSIMOXDRAMlow-voltage operation
 Summary | Full Text:PDF(1MB)

Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
Yasuo YAMAGUCHI Jun TAKAHASHI Takehisa YAMAGUCHI Tomohisa WADA Toshiaki IWAMATSU Hans-Oliver JOACHIM Yasuo INOUE Tadashi NISHIMURA Natsuro TSUBOUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 812-817
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
SOISIMOXSRAMlow-voltage operationback-gate bias effect
 Summary | Full Text:PDF(695.1KB)

Hot-Carrier Reliability in Submicrometer Ultra-Thin SOI-MOSFET's
Yasuo YAMAGUCHI Masahiro SHIMIZU Yasuo INOUE Tadashi NISHIMURA Katsuhiro TSUKAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/12/25
Vol. E75-C  No. 12  pp. 1465-1470
Type of Manuscript:  Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices)
Category: Hot Carrier
Keyword: 
thin SOIhot-carrierSIMOXgate-overlapped LDD
 Summary | Full Text:PDF(582.8KB)