Yasuhiko HAGIHARA


Fingertip-Size Optical Module, “Optical I/O Core”, and Its Application in FPGA
Takahiro NAKAMURA Kenichiro YASHIKI Kenji MIZUTANI Takaaki NEDACHI Junichi FUJIKATA Masatoshi TOKUSHIMA Jun USHIDA Masataka NOGUCHI Daisuke OKAMOTO Yasuyuki SUZUKI Takanori SHIMIZU Koichi TAKEMURA Akio UKITA Yasuhiro IBUSUKI Mitsuru KURIHARA Keizo KINOSHITA Tsuyoshi HORIKAWA Hiroshi YAMAGUCHI Junichi TSUCHIDA Yasuhiko HAGIHARA Kazuhiko KURATA 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4  pp. 333-339
Type of Manuscript:  INVITED PAPER (Special Section on Progress in Optical Device Technology for Increasing Data Transmission Capacity)
Category: 
Keyword: 
silicon photonicsbandwidth densityoptical/electrical assemblyFPGA
 Summary | Full Text:PDF(2.1MB)

25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores
Kenichiro YASHIKI Toshinori UEMURA Mitsuru KURIHARA Yasuyuki SUZUKI Masatoshi TOKUSHIMA Yasuhiko HAGIHARA Kazuhiko KURATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C  No. 2  pp. 148-156
Type of Manuscript:  INVITED PAPER (Special Section on Recent Advances in Photonics Technologies and Their Applications)
Category: 
Keyword: 
Si photonicslow-power-consumptionsmall footprinthigh density interfaceI/O bottleneck
 Summary | Full Text:PDF(3.6MB)

An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques
Masahiro NOMURA Taku OHSAWA Koichi TAKEDA Yoetsu NAKAZAWA Yoshinori HIROTA Yasuhiko HAGIHARA Naoki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 334-341
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interface and Interconnect Techniques
Keyword: 
repeaterbi-directional busautomatic direction controlcollaborative driving technique
 Summary | Full Text:PDF(797.9KB)

Timing Optimization Methodology Based on Replacing Flip-Flops by Latches
Ko YOSHIKAWA Keisuke KANAMARU Yasuhiko HAGIHARA Shigeto INUI Yuichi NAKAMURA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3151-3158
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesissequential circuittiming optimizationlevel-sensitive latchformal verification
 Summary | Full Text:PDF(402.1KB)