Xiao PENG


Dynamic Check Message Majority-Logic Decoding Algorithm for Non-binary LDPC Codes
Yichao LU Xiao PENG Guifen TIAN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/06/01
Vol. E97-A  No. 6  pp. 1356-1364
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
non-binary LDPC codesmajority-logic decodingiterative decodingmessage-passing algorithms
 Summary | Full Text:PDF(1.4MB)

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS
Xiongxin ZHAO Zhixiang CHEN Xiao PENG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2623-2632
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAXbit-serialfully-parallellayered schedulingperformance awareadvanced dynamic quantizationquasi-cycliclow-density parity-check codes
 Summary | Full Text:PDF(2.2MB)

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC
Muchen LI Jinjia ZHOU Dajiang ZHOU Xiao PENG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1366-1375
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
HEVCH.264/AVCdeblocking filterdual-modelow powerSHVHD
 Summary | Full Text:PDF(2.7MB)

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX
Xiongxin ZHAO Xiao PENG Zhixiang CHEN Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2384-2391
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAXbit-seriallayered schedulingQC-LDPC
 Summary | Full Text:PDF(3MB)

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
Zhixiang CHEN Xiao PENG Xiongxin ZHAO Leona OKAMURA Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2587-2596
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WPANIEEE802.15.3cLDPC decoderhigh data ratepower-efficient
 Summary | Full Text:PDF(1.6MB)

Generic Permutation Network for QC-LDPC Decoder
Xiao PENG Xiongxin ZHAO Zhixiang CHEN Fumiaki MAEHARA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2551-2559
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
LDPC decoderreconfigurablepermutation networkparallelism
 Summary | Full Text:PDF(1.2MB)

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
Xiao PENG Zhixiang CHEN Xiongxin ZHAO Fumiaki MAEHARA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 270-278
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
permutationbanyan networkLDPC decoderreconfigurable
 Summary | Full Text:PDF(710.8KB)