Viraphol CHAIYAKUL


Linking Register-Transfer and Physical Levels of Design
Fadi J. KURDAHI Daniel D. GAJSKI Champaka RAMACHANDRAN Viraphol CHAIYAKUL 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 991-1005
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Design
Keyword: 
layoutareadelayestimationhigh-level design
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