Vasily G. MOSHNYAGA


FPGA Design of User Monitoring System for Display Power Control
Tomoaki ANDO Vasily G. MOSHNYAGA Koji HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2364-2372
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
seven-segment rectangular templatebetween the eyes regioneye-detectionuser monitoringFPGAdisplaypower management
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Multiplier Energy Reduction by Dynamic Voltage Variation
Vasily G. MOSHNYAGA Tomoyuki YAMANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3548-3553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Circuit
Keyword: 
multiplierenergy reductiondesign techniquesvoltage scaling
 Summary | Full Text:PDF(683.2KB)

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 862-868
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powercacheleakage
 Summary | Full Text:PDF(1014.7KB)

Reduction of Background Computations in Block-Matching Motion Estimation
Vasily G. MOSHNYAGA Koichi MASUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3  pp. 539-546
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Video/Image Coding
Keyword: 
motion estimationvideo codingcomputational complexityhardware architectureadaptive processing
 Summary | Full Text:PDF(633.3KB)

Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 799-805
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powerinstruction ROMembedded systemsencoding
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Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 279-287
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
cachelow powerlook uprun time
 Summary | Full Text:PDF(726.5KB)

Issue Queue Energy Reduction through Dynamic Voltage Scaling
Vasily G. MOSHNYAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 272-278
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
issue queuecomputer architecturelow powervoltage scaling
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Trends in High-Performance, Low-Power Cache Memory Architectures
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 304-314
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
cachelow powerhigh performancemicroprocessorsurvey
 Summary | Full Text:PDF(238.5KB)

Reducing Cache Energy Dissipation by Using Dual Voltage Supply
Vasily G. MOSHNYAGA Hiroshi TSUJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2762-2768
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
cacheprocessor architecturelow-power
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A Novel Computationally Adaptive Hardware Algorithm for Video Motion Estimation
Vasily G. MOSHNYAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1749-1754
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Imaging Circuits and Algorithms
Keyword: 
video processingmotion estimationhardware algorithmVLSI architecture
 Summary | Full Text:PDF(485.9KB)

A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs
Vasily G. MOSHNYAGA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1389-1395
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high-level synthesisASIC design methodology
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Register-Transfer Module Selection for Sub-Micron ASIC Design
Vasily G. MOSHNYAGA Yutaka MORI Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 252-255
Type of Manuscript:  Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
Category: 
Keyword: 
module selectionregister-transfer synthesis
 Summary | Full Text:PDF(358.9KB)

A Language for Designing Module Generators
Vasily G. MOSHNYAGA Keikichi TAMARU Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1066-1074
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Hardware Design Languages
Keyword: 
module generatorhardware disign language
 Summary | Full Text:PDF(722.8KB)