IEICE SEARCH SYSTEM

Tsuyoshi IWAGAKI

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2563-2570 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: asynchronous on-chip interconnect, CHAIN, stuck-at fault, test scheduling, integer linear programming,
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Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 pp. 1067-1081 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: datapath synthesis, delay variation, register assignment, hold timing constraint, backward-data-direction clocking, integer linear programming,
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Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1096-1105 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: datapath synthesis, delay variation, register assignment, setup and hold constraints, minimum delay compensation, integer linear programming,
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Novel Register Sharing in Datapath for Structural Robustness against Delay Variation Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1044-1053 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: datapath synthesis, delay variation, register assignment, setup and hold constraints,
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A Low Power Deterministic Test Using Scan Chain Disable Technique Zhiqiang YOU Tsuyoshi IWAGAKI Michiko INOUE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/06/01 Vol. E89-D No. 6 pp. 1931-1939 Type of Manuscript: PAPER Category: Dependable Computing Keyword: low power testing, full scan testing, deterministic test, scan chain disable, tabu search algorithm,
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A Design Scheme for Delay Testing of Controllers Using State Transition Information Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3200-3207 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: controller, delay fault, non-scan design, invalid test state and transition generator, at-speed test,
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