Tsutomu SASAO


A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Hisashi IWAMOTO Yasuhiro TERAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2  pp. 262-271
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
CAMIP lookupindex generation unitFPGA
 Summary | Full Text:PDF(1MB)

A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix
Tsutomu SASAO Yuta URANO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2427-2433
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
minimal coverlinear transformationfunctional decompositionincompletely specified functionlogic minimization
 Summary | Full Text:PDF(885.6KB)

Head-Tail Expressions for Interval Functions
Infall SYAFALNI Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/10/01
Vol. E97-A  No. 10  pp. 2043-2054
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
prefix sum-of-productshead-tail expressionsTCAM
 Summary | Full Text:PDF(934.9KB)

A Packet Classifier Based on Prefetching EVMDD (k) Machines
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2243-2252
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
many corepacket classificationdecision diagrammulti-valued logic
 Summary | Full Text:PDF(2.1MB)

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER Mitchell A. THORNTON Theodore W. MANIKAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2234-2242
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
minimization algorithm of the number of edgesEVMDDsgrouping variables for optimization of decision diagramsmulti-state systemssystem analysis using decision diagrams
 Summary | Full Text:PDF(891.9KB)

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1667-1675
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
pattern matchingvirus scanningindex generation functionCAM
 Summary | Full Text:PDF(1.1MB)

On the Numbers of Products in Prefix SOPs for Interval Functions
Infall SYAFALNI Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5  pp. 1086-1094
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
prefix sum-of-productsnumber of products by PreSOPdistribution of interval functionsestimating the size of TCAM
 Summary | Full Text:PDF(828.8KB)

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 364-373
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
regular expressionNFADFAMNFAUFPGA
 Summary | Full Text:PDF(780.2KB)

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2059-2067
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
two-variable numeric function generators (NFGs)edge-valued multiple-valued decision diagrams (EVMDDs)edge-valued binary decision diagrams (EVBDDs)graph-based representation of numeric functionsprogrammable memory-based architecture
 Summary | Full Text:PDF(391KB)

A Quaternary Decision Diagram Machine: Optimization of Its Code
Tsutomu SASAO Hiroki NAKAHARA Munehiro MATSUURA Yoshifumi KAWAMURA Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2026-2035
Type of Manuscript:  INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: 
Keyword: 
quarternary decision diagrambranching program machine
 Summary | Full Text:PDF(650.9KB)

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Yoshifumi KAWAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2048-2058
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
embedded systembranching program machinemulti-processingBDD
 Summary | Full Text:PDF(1MB)

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades
Munehiro MATSUURA Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2762-2769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
incompletely specified functioncharacteristic functionbinary decision diagramfunctional decompositionLUT cascade
 Summary | Full Text:PDF(253.3KB)

Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2752-2761
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
edge-valued binary decision diagrams (EVBDDs)recursive segmentationpiecewise polynomial approximationnumerical function generators (NFGs)programmable architecture
 Summary | Full Text:PDF(411KB)

Design Methods of Radix Converters Using Arithmetic Decompositions
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/06/01
Vol. E90-D  No. 6  pp. 905-914
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
radix converterLUT cascadesFPGAfunctional decomposition
 Summary | Full Text:PDF(456.6KB)

A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5  pp. 932-940
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
three-level networksAND-EXORNP-equivalencecoordinate representationµ-equivalencespectral methodlogic minimization
 Summary | Full Text:PDF(227.1KB)

Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3443-3450
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesisBoolean matchingcell-library bindingtechnology mappingcanonical form
 Summary | Full Text:PDF(326.9KB)

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3471-3481
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
LUT cascadebdd_for_cffunctional decomposition
 Summary | Full Text:PDF(634KB)

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3510-3518
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
LUT cascades2nd-order Chebyshev approximationnon-uniform segmentationNFGsautomatic synthesisFPGA
 Summary | Full Text:PDF(308KB)

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA
Hui QIN Tsutomu SASAO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1139-1147
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
AES encryptionpipelined partial rolling (PPR)FPGA
 Summary | Full Text:PDF(1.3MB)

A Design Algorithm for Sequential Circuits Using LUT Rings
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3342-3350
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
reconfigurable architectureLUT cascadeBDD_for_CFfunctional decomposition
 Summary | Full Text:PDF(699.9KB)

Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3332-3341
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
AND-EXORReed-Muller expressionFPRMexact minimizationincompletely specified function
 Summary | Full Text:PDF(549.7KB)

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1492-1500
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
three-level networklogic minimizationadderprogrammable logic
 Summary | Full Text:PDF(724.5KB)

Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3134-3140
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
Boolean matchingtechnology mappingvariable permutationP-equivalence
 Summary | Full Text:PDF(691.5KB)

A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3141-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
LUT cascadeLUT ringmultiple-output functionreconfigurable logicprogrammable logic device
 Summary | Full Text:PDF(675.1KB)

Area-Time Complexities of Multi-Valued Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Yukihiro IGUCHI Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Vol. E87-A  No. 5  pp. 1020-1028
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
decision diagramsthe number of nodesarea-time complexityrandomly generated functionrepresentation of logic functions
 Summary | Full Text:PDF(307.2KB)

Fault Diagnosis for RAMs Using Walsh Spectrum
Atsumu ISENO Yukihiro IGUCHI Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 592-600
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Memory Testing
Keyword: 
memory testdiagnosisBISTfail-bitmapWalsh spectrum
 Summary | Full Text:PDF(717.5KB)

Compact Representations of Logic Functions Using Heterogeneous MDDs
Shinobu NAGAYAMA Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3168-3175
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
heterogeneous MDDROBDDFBDDAPLmemory size
 Summary | Full Text:PDF(192.4KB)

Bi-Partition of Shared Binary Decision Diagrams
Munehiro MATSUURA Tsutomu SASAO Jon T. BUTLER Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2693-2700
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
shared binary decision diagramSBDDbi-partitionmultiple-output functiondecomposition
 Summary | Full Text:PDF(555.1KB)

Heuristics to Minimize Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2498-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD)multiple-valued decision diagram (MDD)multiple-output functionmultiple-valued logicFPGA design
 Summary | Full Text:PDF(451.2KB)

Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2398-2406
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagram (BDD)characteristic function (CF)multiple-output functionvariable orderinglogic simulationadderbit-counting functionmultiplier
 Summary | Full Text:PDF(563.6KB)

FOREWORD
Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5  pp. 909-909
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(74.9KB)

Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5  pp. 925-932
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Logic Design
Keyword: 
multiple-valued decision diagram (MDD)multiple-valued logicmultiple-output functiontime-division multiplexing (TDM)
 Summary | Full Text:PDF(411.7KB)

Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2545-2553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD)multiple-output functions clique coverTDM realizationlogic simulation
 Summary | Full Text:PDF(652.7KB)

On Properties of Kleene TDDs
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 716-723
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword: 
binary decision diagramternary decision diagramlogic simulationternary logic
 Summary | Full Text:PDF(631.4KB)

Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 1001-1008
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
three-level networksAND-EXORlogic minimizationcomplexity of logic networksNP-equivalence
 Summary | Full Text:PDF(651.2KB)

FOREWORD
Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 973-973
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(75.3KB)

Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm
Tsutomu SASAO Debatosh DEBNATH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2123-2130
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
AND-EXORReed-Muller expressioncomplexity of logic networkslogic minimizationbinary decision diagramseasily testable networks
 Summary | Full Text:PDF(621.2KB)

Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams
Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5  pp. 562-570
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Logic Design
Keyword: 
Reed-Muller expressionAND-EXOR expressionlogic minimizationbinary decision diagramsymmetric functions
 Summary | Full Text:PDF(650.3KB)