Tsutomu MARUYAMA


An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA
Kenji KANAZAWA Tsutomu MARUYAMA 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1807-1818
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGASATMaxSATWalkSAT
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A Fast and Accurate FPGA System for Short Read Mapping Based on Parallel Comparison on Hash Table
Yoko SOGABE Tsutomu MARUYAMA 
Publication:   
Publication Date: 2017/05/01
Vol. E100-D  No. 5  pp. 1016-1025
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
field programmable gate arraygenome sequence alignmentaccelerated implementationbioinformatics
 Summary | Full Text:PDF(1.1MB)

FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm
Henry BLOCK Tsutomu MARUYAMA 
Publication:   
Publication Date: 2017/02/01
Vol. E100-D  No. 2  pp. 256-264
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGAhardware accelerationphylogenetic tree reconstructionmaximum parsimony
 Summary | Full Text:PDF(899.3KB)

Multiple Sequence Alignment Based on Dynamic Programming Using FPGA
Shingo MASUNO Tsutomu MARUYAMA Yoshiki YAMAGUCHI Akihiko KONAGAYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1939-1946
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
multiple sequence alignmentdynamic programmingFPGAreconfiguration
 Summary | Full Text:PDF(436.1KB)