Tsunemichi SHIOZAWA

Programmable Dataflow Computing on PCA
Norbert IMLIG  Tsunemichi SHIOZAWA  Ryusuke KONISHI  Kiyoshi OGURI  Kouichi NAGAMI  Hideyuki ITO  Minoru INAMORI  Hiroshi NAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/20
Vol. E83-A  No. 12  pp. 2409-2416
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
programmable logic devices,  dataflow computing,  parallel processing,  plastic cell architecture, 
  Summary |  Full Text:PDF (544.3KB)
Plastic Cell Architecture: A Scalable Device Architecture for General-Purpose Reconfigurable Computing
Kouichi NAGAMI  Kiyoshi OGURI  Tsunemichi SHIOZAWA  Hideyuki ITO  Ryusuke KONISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/20
Vol. E81-C  No. 9  pp. 1431-1437
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
reconfigurable computing,  FPGAs,  object-oriented,  hardware description language,  cellular automata, 
  Summary |  Full Text:PDF (690.5KB)
Inverter Reduction Algorithm for Super Fine-Grain Parallel Processing
Hideyuki ITO  Kouichi NAGAMI  Tsunemichi SHIOZAWA  Kiyoshi OGURI  Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/20
Vol. E80-A  No. 3  pp. 487-493
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
super fine-grain parallel processing,  FPGA,  high level synthesize PARTHENON,  inverter reduction,  dynamical system, 
  Summary |  Full Text:PDF (573.6KB)