Toshiro HIRAMOTO


Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress
Toshiro HIRAMOTO Anil KUMAR Takuya SARAYA Shinji MIYANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6  pp. 759-765
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
transistorMOSFETvariabilityoff-state stress
 Summary | Full Text:PDF(3.5MB)

NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM
Nurul Ezaila ALIAS Anil KUMAR Takuya SARAYA Shinji MIYANO Toshiro HIRAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/05/01
Vol. E96-C  No. 5  pp. 620-623
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
Negative Bias Temperature Instability (NBTI)variabilitySRAMtransistorMOSFET
 Summary | Full Text:PDF(1.1MB)

Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs
Tomoko MIZUTANI Anil KUMAR Toshiro HIRAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/05/01
Vol. E96-C  No. 5  pp. 630-633
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
variabilityMOS transistorthreshold voltageDIBLnormal distributionGumbel distribution
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Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations
Toshiro HIRAMOTO Toshiharu NAGUMO Tetsu OHTOU Kouki YOKOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 836-841
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: 
Keyword: 
SOIbody factorbody effectFinFETmultigate MOSFET
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Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs
Toshiki SAITO Takuya SARAYA Takashi INUKAI Hideaki MAJIMA Toshiharu NAGUMO Toshiro HIRAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5  pp. 1073-1078
Type of Manuscript:  Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
Category: 
Keyword: 
SOI MOSFETtriangular wireshort channel effectsubthreshold factorDIBL
 Summary | Full Text:PDF(1MB)

FOREWORD
Toshiro HIRAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5  pp. 1051-1051
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(40.2KB)

Effects of Discrete Quantum Levels on Electron Transport in Silicon Single-Electron Transistors with an Ultra-Small Quantum Dot
Masumi SAITOH Toshiro HIRAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/08/01
Vol. E84-C  No. 8  pp. 1071-1076
Type of Manuscript:  Special Section PAPER (Special Issue on Silicon Nanodevices)
Category: 
Keyword: 
silicon single-electron transistorultra-small quantum dotquantum level spacingfine structuresnegative differential conductance
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Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias
Toshiro HIRAMOTO Makoto TAKAMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 161-169
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
MOSFETlow powerlow voltagevariable threshold voltageback-biasbody effectDTMOSSOI
 Summary | Full Text:PDF(887.3KB)

A Bipolar-Based 0.5 µm BiCMOS Technology on Bonded SOI for High-Speed LSIs
Makoto YOSHIDA Toshiro HIRAMOTO Tsuyoshi FUJIWARA Takashi HASHIMOTO Tetsuya MURAYA Shigeharu MURATA Kunihiko WATANABE Nobuo TAMBA Takahide IKEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1395-1403
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: General Technology
Keyword: 
BiCMOSbonded SOIdouble polysilicon bipolartrench isolationstress
 Summary | Full Text:PDF(1.1MB)

A 1.5-ns Cycle-Time 18-kb Pseudo-Dual-Port RAM with 9K Logic Gates
Masato IWABUCHI Masami USAMI Masamori KASHIYAMA Takashi OOMORI Shigeharu MURATA Toshiro HIRAMOTO Takashi HASHIMOTO Yasuhiro NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 749-755
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(597.6KB)