Toshinori HOSOKAWA


A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution
Hiroshi YAMAZAKI Motohiro WAKAZONO Toshinori HOSOKAWA Masayoshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1994-2002
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
X-bitdon't care identificationX-bit distributiontest compaction
 Summary | Full Text:PDF(1.4MB)

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
Ryoichi INOUE Toshinori HOSOKAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 24-32
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
state-observable FSMslogical fault testingtiming fault testingfault sensitization coveragen-detection
 Summary | Full Text:PDF(2.1MB)

A DFT Selection Method for Reducing Test Application Time of System-on-Chips
Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 609-619
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test schedulingtest access mechanismwrapperdesign for test
 Summary | Full Text:PDF(2.2MB)

A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
Toshinori HOSOKAWA Hiroshi DATE Masahide MIYAZAKI Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2674-2683
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test plan groupingtest controllerspartly compacted test plan tablesRTL data pathshierarchical test generation
 Summary | Full Text:PDF(1.1MB)

Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits
Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1474-1482
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test Generation and Modification
Keyword: 
test generationtest planscompacted test plan tablestest plan compatibility graphRTL data path
 Summary | Full Text:PDF(1.2MB)

Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time
Toshinori HOSOKAWA Masayoshi YOSHIMURA Mitsuyasu OHTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2722-2730
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
DFT strategiesfull scan design methodspartial scan design methodstest point insertionstest application time
 Summary | Full Text:PDF(1.3MB)

Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops
Toshinori HOSOKAWA Toshihiro HIRAOKA Mitsuyasu OHTA Michiaki MURAOKA Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 660-667
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
design for testabilitypartial scan design methodn-fold line-up structurepure load/hold FF
 Summary | Full Text:PDF(715.5KB)