Toshiaki SHIMADA


A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores
Tetsuya MATSUMURA Satoshi KUMAKI Hiroshi SEGAWA Kazuya ISHIHARA Atsuo HANAMI Yoshinori MATSUURA Stefan SCOTZNIOVSKY Hidehiro TAKATA Akira YAMADA Shu MURAYAMA Tetsuro WADA Hideo OHIRA Toshiaki SHIMADA Ken-ichi ASANO Toyohiko YOSHIDA Masahiko YOSHIMOTO Koji TSUCHIHASHI Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/01/01
Vol. E84-C  No. 1  pp. 108-122
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
video encoderMPEG-2media-processoraudio encodersystem encodermotion estimation
 Summary | Full Text:PDF(2.1MB)

An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
Shin-ichi URAMOTO Akihiko TAKABATAKE Takashi HASHIMOTO Jun TAKEDA Gen-ichi TANAKA Tsuyoshi YAMADA Yukio KODAMA Atsushi MAEDA Toshiaki SHIMADA Shun-ichi SEKIGUCHI Tokumichi MURAKAMI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12  pp. 1697-1708
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
image compressionvideo decoderMPEG2
 Summary | Full Text:PDF(1.1MB)