Toshiaki KITAMURA

Development of a Power Efficient SMT Processor with Heterogeneous Instruction Set Architectures
Kazuhiro YOSHIMURA  Takashi NAKADA  Yasuhiko NAKASHIMA  Toshiaki KITAMURA 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2012/06/01
Vol. J95-D  No. 6  pp. 1334-1346
Type of Manuscript: PAPER
Category: 
Keyword: 
VLIW/superscalar mixed architecture,  multithreading,  LSI prototyping,  processor development environment, 
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