Tomoo INOUE


Hybrid Test Application in Partial Skewed-Load Scan Design
Yuki YOSHIKAWA Tomomi NUWA Hideyuki ICHIHARA Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2571-2578
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
delay testingdesign-for-testabilityskewed-load test applicationbroad-side test applicationpartial skewed-load scan designhybrid test application
 Summary | Full Text:PDF(782.1KB)

A Practical Threshold Test Generation for Error Tolerant Application
Hideyuki ICHIHARA Kenta SUTOH Yuki YOSHIKAWA Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/10/01
Vol. E93-D  No. 10  pp. 2776-2782
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
acceptable faulttest generation modelerror significancethreshold testing and error tolerance
 Summary | Full Text:PDF(394.4KB)

Design and Optimization of Transparency-Based TAM for SoC Test
Tomokazu YONEDA Akiko SHUTO Hideyuki ICHIHARA Tomoo INOUE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/06/01
Vol. E93-D  No. 6  pp. 1549-1559
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
SoC testdesign for testabilityTAM designtransparencyILP
 Summary | Full Text:PDF(563.8KB)

An Architecture of Embedded Decompressor with Reconfigurability for Test Compression
Hideyuki ICHIHARA Tomoyuki SAIKI Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 713-719
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Test Compression
Keyword: 
test compressionATEreconfigurabilityvariable-length codingtest application
 Summary | Full Text:PDF(408.7KB)

A Self-Test of Dynamically Reconfigurable Processors with Test Frames
Tomoo INOUE Takashi FUJII Hideyuki ICHIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 756-762
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
dynamically reconfigurable processorsself-testoptimal contextstest application timetest frames
 Summary | Full Text:PDF(792.3KB)

A Variable-Length Coding Adjustable for Compressed Test Application
Hideyuki ICHIHARA Toshihiro OHARA Michihiro SHINTANI Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/08/01
Vol. E90-D  No. 8  pp. 1235-1242
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test compressionvariable-length codingtest application timeATEHuffman codeand test environment
 Summary | Full Text:PDF(309.9KB)

Huffman-Based Test Response Coding
Hideyuki ICHIHARA Michihiro SHINTANI Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/01/01
Vol. E88-D  No. 1  pp. 158-161
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
Huffman codetest compressiontest responsetest application timeATE
 Summary | Full Text:PDF(103.9KB)

A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
Hideyuki ICHIHARA Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3072-3078
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
test generationacyclic sequential circuitsstuck-at faultpartial scanmultiple fault
 Summary | Full Text:PDF(383.3KB)

Test Generation for Test Compression Based on Statistical Coding
Hideyuki ICHIHARA Atsuhiro OGAWA Tomoo INOUE Akio TAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1466-1473
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test Generation and Modification
Keyword: 
VLSI testtest compressionstatistical codetest generationautomatic test equipment
 Summary | Full Text:PDF(298.2KB)

Testing for the Programming Circuit of SRAM-Based FPGAs
Hiroyuki MICHINISHI Tokumi YOKOHIRA Takuji OKAMOTO Tomoo INOUE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/06/25
Vol. E82-D  No. 6  pp. 1051-1057
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault detectionLUT-based FPGASRAM-based FPGAfunctional faultconfiguration
 Summary | Full Text:PDF(608.4KB)

Performance Analysis of Parallel Test Generation for Combinational Circuits
Tomoo INOUE Takaharu FUJII Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/25
Vol. E79-D  No. 9  pp. 1257-1265
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
test generationparallel processingperformance analysisinterprocessor communicationspeedup
 Summary | Full Text:PDF(723KB)

On the Effect of Scheduling in Test Generation
Tomoo INOUE Hironori MAEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1190-1197
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
test generationtest generation schedulefault orderingfault dominancecost of testing
 Summary | Full Text:PDF(654.7KB)