Tomonori SEKIGUCHI


Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
Akira KOTABE  Riichiro TAKEMURA  Yoshimitsu YANAGAWA  Tomonori SEKIGUCHI  Kiyoo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 594-599
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DRAMlow voltagesense amplifiermid-point sensing
  Summary |  Full Text:PDF (2.3MB)

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
Satoru AKIYAMA  Riichiro TAKEMURA  Tomonori SEKIGUCHI  Akira KOTABE  Kiyoo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 600-608
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-voltage DRAMgated preamplifiermid-point sensingvariations in threshold voltage
  Summary |  Full Text:PDF (2MB)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation
Riichiro TAKEMURA  Kiyoo ITOH  Tomonori SEKIGUCHI  Satoru AKIYAMA  Satoru HANZAWA  Kazuhiko KAJIGAYA  Takayuki KAWAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 758-764
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
twin-cell DRAM arraywrite timelow voltage RAMretention timeand plate-driven cell
  Summary |  Full Text:PDF (1.6MB)

A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory
Satoru HANZAWA  Takeshi SAKATA  Tomonori SEKIGUCHI  Hideyuki MATSUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/09/01
Vol. E86-C  No. 9  pp. 1886-1893
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
emerging memoryMISS tunnel-diodehierarchical bit-line structuretwin dummy-cell
  Summary |  Full Text:PDF (1.8MB)

A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
Hiroki FUJISAWA  Takeshi SAKATA  Tomonori SEKIGUCHI  Kazuyoshi TORII  Katsutaka KIMURA  Kazuhiko KAJIGAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6  pp. 763-770
Type of Manuscript: Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
DRAMferroelectric memoryhigh speedlow-powerhigh-endurance
  Summary |  Full Text:PDF (777.3KB)

Calculation of the Potential Distribution around an Impurity-Atom-Wire--The Validity of the Thomas-Fermi Approximation--
Tomonori SEKIGUCHI  Kazuhito FURUYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/20
Vol. E76-C  No. 12  pp. 1842-1846
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
impurity-atom-wirequantum wirenanometer structurescreening effectelectron wave
  Summary |  Full Text:PDF (368.8KB)