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Tomohisa WADA

Pilot-Aided Channel Estimation for WiMAX 802.16e Downlink Partial Usage of Subchannel System Using Least Squares Line Fitting Phuong Thi Thu PHAM Tomohisa WADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2010/06/01 Vol. E93-B No. 6 pp. 1494-1501 Type of Manuscript: PAPER Category: Wireless Communication Technologies Keyword: channel estimation, IEEE 802.16e, OFDMA, downlink PUSC, least squares line fitting,
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Joint Hardware-Software Implementation of Adaptive Array Antenna for ISDB-T Reception Dang Hai PHAM Takanobu TABATA Hirokazu ASATO Satoshi HORI Tomohisa WADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2006/12/01 Vol. E89-B No. 12 pp. 3215-3224 Type of Manuscript: Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications) Category: Keyword: array antenna, OFDM, ISDB-T, MRC, SMI, FPGA, DSP,
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A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology Kunihiko KOZARU Atsushi KINOSHITA Tomohisa WADA Yutaka ARITA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/20 Vol. E80-C No. 4 pp. 566-572 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: super-CMOS, high-speed SRAM, reference voltage generator, voltage down converter,
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111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/20 Vol. E79-C No. 6 pp. 735-742 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: memory, synchronous SRAM, high speed SRAM, low power, clock,
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A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/20 Vol. E79-C No. 6 pp. 743-749 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: integrated electronics, high density SRAM, hierarchical bit line organization, T-shaged bit line,
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Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect Yasuo YAMAGUCHI Jun TAKAHASHI Takehisa YAMAGUCHI Tomohisa WADA Toshiaki IWAMATSU Hans-Oliver JOACHIM Yasuo INOUE Tadashi NISHIMURA Natsuro TSUBOUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/20 Vol. E78-C No. 7 pp. 812-817 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: SOI, SIMOX, SRAM, low-voltage operation, back-gate bias effect,
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A New Soft-Error Phenomenon is ULSI SRAM's--Inverted Dependence of Soft-Error Rate on Cycle Time-- Shuji MURAKAMI Tomohisa WADA Masanao EINO Motomu UKITA Yasumasa NISHIMURA Kimio SUZUKI Kenji ANAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/20 Vol. E74-C No. 4 pp. 853-858 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: SRAM Keyword:
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A Study on Fanout Optimization of SRAM Decoder with a Line Capacitance Shigeki OHBAYASHI Tomohisa WADA Toshihiko HIROSE Kenji ANAMI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/11/20 Vol. E73-E No. 11 pp. 1855-1857 Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE) Category: Integrated Circuits Keyword:
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