Tomohisa WADA


Pilot-Aided Channel Estimation for WiMAX 802.16e Downlink Partial Usage of Subchannel System Using Least Squares Line Fitting
Phuong Thi Thu PHAM Tomohisa WADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/06/01
Vol. E93-B  No. 6  pp. 1494-1501
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
channel estimationIEEE 802.16eOFDMAdownlink PUSCleast squares line fitting
 Summary | Full Text:PDF(3.7MB)

Joint Hardware-Software Implementation of Adaptive Array Antenna for ISDB-T Reception
Dang Hai PHAM Takanobu TABATA Hirokazu ASATO Satoshi HORI Tomohisa WADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/12/01
Vol. E89-B  No. 12  pp. 3215-3224
Type of Manuscript:  Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
array antennaOFDMISDB-TMRCSMIFPGADSP
 Summary | Full Text:PDF(1.1MB)

A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology
Kunihiko KOZARU Atsushi KINOSHITA Tomohisa WADA Yutaka ARITA Michihiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 566-572
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
super-CMOShigh-speed SRAMreference voltage generatorvoltage down converter
 Summary | Full Text:PDF(583.1KB)

A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die
Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 743-749
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
integrated electronicshigh density SRAMhierarchical bit line organizationT-shaged bit line
 Summary | Full Text:PDF(796.2KB)

111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method
Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 735-742
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
memorysynchronous SRAMhigh speed SRAM, low powerclock
 Summary | Full Text:PDF(823.7KB)

Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
Yasuo YAMAGUCHI Jun TAKAHASHI Takehisa YAMAGUCHI Tomohisa WADA Toshiaki IWAMATSU Hans-Oliver JOACHIM Yasuo INOUE Tadashi NISHIMURA Natsuro TSUBOUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 812-817
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
SOISIMOXSRAMlow-voltage operationback-gate bias effect
 Summary | Full Text:PDF(695.1KB)

A New Soft-Error Phenomenon is ULSI SRAM's--Inverted Dependence of Soft-Error Rate on Cycle Time--
Shuji MURAKAMI Tomohisa WADA Masanao EINO Motomu UKITA Yasumasa NISHIMURA Kimio SUZUKI Kenji ANAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 853-858
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: SRAM
Keyword: 
 Summary | Full Text:PDF(603.6KB)

A Study on Fanout Optimization of SRAM Decoder with a Line Capacitance
Shigeki OHBAYASHI Tomohisa WADA Toshihiko HIROSE Kenji ANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1855-1857
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF(176.1KB)