Tokuo KURE


A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
Masataka MINAMI Nagatoshi OHKI Hiroshi ISHIDA Toshiaki YAMANAKA Akihiro SHIMIZU Koichiro ISHIBASHI Akira SATOH Tokuo KURE Takashi NISHIDA Takahiro NAGANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 590-596
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMfull CMOS celllocal interconnectTiN
 Summary | Full Text:PDF(635.1KB)

Recessed Memory Array Technology for a Double Cylindrical Stacked Capacitor Cell of 256M DRAM
Kazuhiko SAGARA Tokuo KURE Shoji SHUKURI Jiro YAGAMI Norio HASEGAWA Hidekazu GOTO Hisaomi YAMASHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1313-1322
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
recessed memory arraystacked capacitor cell256 MDRAM
 Summary | Full Text:PDF(1.5MB)