Tohru ISHIHARA


A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation
Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2764-2775
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
minimum energy point tracking (MEPT)dynamic voltage and frequency scaling (DVFS)adaptive body biasing (ABB)standard-cell based memory (SCM)
 Summary | Full Text:PDF(2MB)

A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing
Shu HOKIMOTO Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2776-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
minimum energy point tracking (MEPT)dynamic voltage and frequency scaling (DVFS)adaptive body biasing (ABB)
 Summary | Full Text:PDF(1.4MB)

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation
Tatsuya KAMAKARI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2463-2472
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
latchlow voltage designstability modeling
 Summary | Full Text:PDF(2.9MB)

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization
Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1455-1466
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
near-threshold computingstatistical static timing analysis (SSTA)
 Summary | Full Text:PDF(1.7MB)

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications
Hideki TAKASE Gang ZENG Lovic GAUTHIER Hirotaka KAWASHIMA Noritoshi ATSUMI Tomohiro TATEMATSU Yoshitake KOBAYASHI Takenori KOSHIRO Tohru ISHIHARA Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2477-2487
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
energy optimizationcompilerprofilerreal-time operating systemsembedded systems
 Summary | Full Text:PDF(7.3MB)

DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems
Kyungsoo LEE Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2660-2667
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
task schedulingpower loss reductionDC-DC converterenergy harvestingreconfigurablePV cellsupercapacitor
 Summary | Full Text:PDF(2.3MB)

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation
Shinichi NISHIZAWA Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2499-2507
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
standard cell designlow power circuit designnear threshold operationPN ratio optimization
 Summary | Full Text:PDF(2MB)

Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications
Lovic GAUTHIER Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2597-2608
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
stackscratch-pad memoryenergy consumption reductionembedded systems
 Summary | Full Text:PDF(1.9MB)

A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems
Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2533-2541
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
microprocessorlow-power designembedded systemsreal-time systems
 Summary | Full Text:PDF(741.9KB)

Way-Scaling to Reduce Power of Cache with Delay Variation
Maziar GOUDARZI Tadayuki MATSUMURA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3576-3584
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
leakagepower reductioncachewithin-die variationdelay variationway scaling
 Summary | Full Text:PDF(1.3MB)

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 410-417
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
single event upsetSRAMDRAMreliabilitycache architecturetask scheduling
 Summary | Full Text:PDF(558.2KB)

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1983-1991
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Design Technology
Keyword: 
soft errorreliabilityestimationcomputer systemsinstruction-set simulation
 Summary | Full Text:PDF(670.7KB)

A System Level Optimization Technique for Application Specific Low Power Memories
Tohru ISHIHARA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2755-2761
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
low power designhardware/software codesignmemorylow voltageembedded system
 Summary | Full Text:PDF(557.2KB)

A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection
Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 186-194
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
cachelow powerlow energyway predictionhigh performance
 Summary | Full Text:PDF(1015.4KB)

System LSI Design Methods for Low Power LSIs
Hiroto YASUURA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 143-152
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
low power designsystem leveloptimizationhardware/software codesign
 Summary | Full Text:PDF(801.9KB)

A Memory Power Optimization Technique for Application Specific Embedded Systems
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2366-2374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
low power designhardware/software codesignmemoryembedded system
 Summary | Full Text:PDF(1.3MB)

Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2621-2629
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
compiler optimizationinstruction schedulinglow powercaches
 Summary | Full Text:PDF(762.4KB)

Programmable Power Management Architecture for Power Reduction
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1473-1480
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
low power designpower managementCMOS VLSI processor
 Summary | Full Text:PDF(677.5KB)

Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 480-486
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
CMOS VLSI circuitslow power designpower estimation
 Summary | Full Text:PDF(520.2KB)