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Tetsuya IIZUKA

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme Kazutoshi KODAMA Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/12/01 Vol. E95-C No. 12 pp. 1857-1863 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: DCO, ADPLL, high frequency resolution enhancement,
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A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology Tetsuya IIZUKA Satoshi MIURA Ryota YAMAMOTO Yutaka CHIBA Shunichi KUBO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 661-667 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: time-to-digital converter, pulse shrinking, buffer ring,
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All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator Tetsuya IIZUKA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 627-634 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: process variability, all digital, on-chip monitor, buffer ring,
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1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells Shingo MANDAI Tetsuya IIZUKA Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1098-1104 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-to-digital converter, TDC, time-difference-amplifier, TDA, time amp,
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All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter Tetsuya IIZUKA Jaehyun JEONG Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 487-494 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: process variability, all digital, on-chip monitor, buffer ring, NBTI, PBTI,
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Cascaded Time Difference Amplifier with Differential Logic Delay Cell Shingo MANDAI Toru NAKURA Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 654-662 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: time-difference-amplifier, TDA, time amp,
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Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3485-3491 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: exact minimum-width transistor placement, Boolean Satisfiability, non-dual CMOS cells,
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Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/07/01 Vol. E88-A No. 7 pp. 1957-1963 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: comprehensive cell layout synthesis, CMOS logic cell, critical area, defect sensitivity, yield optimization,
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High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3293-3300 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: high speed, cell layout synthesis, Boolean Satisfiability, SAT, CMOS logic cell, minimum width,
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A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array Kazuhiro SAWADA Toshinari TAKAYANAGI Kazutaka NOGAMI Makoto TAKAHASHI Masanori UCHIDA Yukiko ITOH Tetsuya IIZUKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/20 Vol. E74-C No. 4 pp. 929-937 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: ASIC Keyword:
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