Tetsuya IIZUKA


A PLL Compiler from Specification to GDSII
Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2741-2749
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
PLL compilerPLL synthesisPWPLLspecification to GDSII
 Summary | Full Text:PDF(2.1MB)

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring
Tomohiko YANO Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA 
Publication:   
Publication Date: 2017/09/01
Vol. E100-C  No. 9  pp. 736-745
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
time-mode circuitanalog front endintegratoraccumulatortime domaincalibration free
 Summary | Full Text:PDF(1.4MB)

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR
Parit KANJANAVIROJKUL Nguyen NGOC MAI-KHANH Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA 
Publication:   
Publication Date: 2017/01/01
Vol. E100-A  No. 1  pp. 200-209
Type of Manuscript:  Special Section PAPER (Special Section on Wideband Systems)
Category: 
Keyword: 
pulse generationUWB-IRCMOSlow duty cycleenergy efficiencyflip-chip devices
 Summary | Full Text:PDF(4MB)

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing
Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/08/01
Vol. E97-A  No. 8  pp. 1688-1698
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Electron Beam Direct WritingCharacter ProjectionroutinginterconnectVIA
 Summary | Full Text:PDF(2.3MB)

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2458-2466
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
electron beam direct writingcharacter projectionVIAinterconnectrouting
 Summary | Full Text:PDF(2.1MB)

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme
Kazutoshi KODAMA Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12  pp. 1857-1863
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
DCOADPLLhigh frequency resolution enhancement
 Summary | Full Text:PDF(2.1MB)

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator
Tetsuya IIZUKA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 627-634
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
process variabilityall digitalon-chip monitorbuffer ring
 Summary | Full Text:PDF(2.2MB)

A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology
Tetsuya IIZUKA Satoshi MIURA Ryota YAMAMOTO Yutaka CHIBA Shunichi KUBO Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 661-667
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
time-to-digital converterpulse shrinkingbuffer ring
 Summary | Full Text:PDF(4MB)

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
Shingo MANDAI Tetsuya IIZUKA Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1098-1104
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
time-to-digital converterTDCtime-difference-amplifierTDAtime amp
 Summary | Full Text:PDF(1.3MB)

Cascaded Time Difference Amplifier with Differential Logic Delay Cell
Shingo MANDAI Toru NAKURA Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 654-662
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
time-difference-amplifierTDAtime amp
 Summary | Full Text:PDF(888.9KB)

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
Tetsuya IIZUKA Jaehyun JEONG Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 487-494
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
process variabilityall digitalon-chip monitorbuffer ringNBTIPBTI
 Summary | Full Text:PDF(1.1MB)

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3485-3491
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
exact minimum-width transistor placementBoolean Satisfiabilitynon-dual CMOS cells
 Summary | Full Text:PDF(265.8KB)

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7  pp. 1957-1963
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
comprehensive cell layout synthesisCMOS logic cellcritical areadefect sensitivityyield optimization
 Summary | Full Text:PDF(408.6KB)

High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3293-3300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
high speedcell layout synthesisBoolean SatisfiabilitySATCMOS logic cellminimum width
 Summary | Full Text:PDF(511.5KB)

A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array
Kazuhiro SAWADA Toshinari TAKAYANAGI Kazutaka NOGAMI Makoto TAKAHASHI Masanori UCHIDA Yukiko ITOH Tetsuya IIZUKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 929-937
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: ASIC
Keyword: 
 Summary | Full Text:PDF(819.7KB)