Tetsushi TANIZAKI

An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester
Naoya WATANABE  Fukashi MORISHITA  Yasuhiko TAITO  Akira YAMAZAKI  Tetsushi TANIZAKI  Katsumi DOSAKA  Yoshikazu MOROOKA  Futoshi IGAUE  Katsuya FURUE  Yoshihiro NAGURA  Tatsunori KOMOIKE  Toshinori MORIHARA  Atsushi HACHISUKA  Kazutami ARIMOTO  Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 624-634
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
embedded DRAM,  various DRAM macros,  low voltage operation,  short TAT,  BIST, 
  Summary |  Full Text:PDF (5.2MB)
Accomplishment of At-Speed BISR for Embedded DRAMs
Yoshihiro NAGURA  Yoshinori FUJIWARA  Katsuya FURUE  Ryuji OHMURA  Tatsunori KOMOIKE  Takenori OKITAKA  Tetsushi TANIZAKI  Katsumi DOSAKA  Kazutami ARIMOTO  Yukiyoshi KODA  Tetsuo TADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1498-1505
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
Keyword: 
at-speed test,  BISR,  embedded DRAM,  test cost reduction, 
  Summary |  Full Text:PDF (2.2MB)