Tatsuo HIGUCHI


Score-Level Fusion of Phase-Based and Feature-Based Fingerprint Matching Algorithms
Koichi ITO Ayumi MORITA Takafumi AOKI Hiroshi NAKAJIMA Koji KOBAYASHI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/03/01
Vol. E93-A  No. 3  pp. 607-616
Type of Manuscript:  PAPER
Category: Image
Keyword: 
fingerprint recognitionphase-only correlationfeature-based matchingcombination of matchersscore-level fusionbiometrics
 Summary | Full Text:PDF(844.1KB)

Arithmetic Circuit Verification Based on Symbolic Computer Algebra
Yuki WATANABE Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/10/01
Vol. E91-A  No. 10  pp. 3038-3046
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
datapatharithmetic circuitsformal verificationcomputer algebra
 Summary | Full Text:PDF(754.8KB)

A Palmprint Recognition Algorithm Using Phase-Only Correlation
Koichi ITO Takafumi AOKI Hiroshi NAKAJIMA Koji KOBAYASHI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1023-1030
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
biometricspalmprint recognitionsecurityimage recognitionphase-only correlation
 Summary | Full Text:PDF(2.9MB)

Formal Design of Arithmetic Circuits Based on Arithmetic Description Language
Naofumi HOMMA Yuki WATANABE Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3500-3509
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
datapathsformal designarithmetic circuitshardware algorithmshardware description languagemodule generator
 Summary | Full Text:PDF(874.3KB)

Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic
Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1645-1654
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
datapathsarithmetic circuitsaddition algorithmsnumber systemsmultiple-valued logic
 Summary | Full Text:PDF(856KB)

A Shortest Path Search Algorithm Using an Excitable Digital Reaction-Diffusion System
Koichi ITO Masahiko HIRATSUKA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/03/01
Vol. E89-A  No. 3  pp. 735-743
Type of Manuscript:  Special Section PAPER (Special Section on Multidimensional Signal Processing and Its Application)
Category: Signal Processing Algorithm
Keyword: 
reaction-diffusion systemnonlinear dynamicsshortest path searchexcitable dynamics
 Summary | Full Text:PDF(2.5MB)

A Redox Microarray--An Experimental Model for Molecular Computing Integrated Circuits--
Masahiko HIRATSUKA Shigeru IKEDA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1804-1808
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
molecular electronicsmolecular computingreaction-diffusion dynamicsnonlinear dynamicsanalog integrated circuits
 Summary | Full Text:PDF(2.4MB)

A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1827-1836
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistorsmultiple-valued logicquantum deviceslogic circuitsparallel counters
 Summary | Full Text:PDF(1.1MB)

A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
Hiroshi INOKAWA Yasuo TAKAHASHI Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1818-1826
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistor (SET)multiple-valued logic (MVL)counteranalytical modelSPICE
 Summary | Full Text:PDF(646.3KB)

A Sub-Pixel Correspondence Search Technique for Computer Vision Applications
Kenji TAKITA Mohammad Abdul MUQUIT Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/08/01
Vol. E87-A  No. 8  pp. 1913-1923
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Image/Visual Signal Processing
Keyword: 
phase-only correlationphase correlationimage matchingsub-pixel matchingblock matching
 Summary | Full Text:PDF(999.8KB)

A Fingerprint Matching Algorithm Using Phase-Only Correlation
Koichi ITO Hiroshi NAKAJIMA Koji KOBAYASHI Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3  pp. 682-691
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Digital Signal Processing for Pattern Recognition
Keyword: 
phase-only correlationphase-only matched filteringphase correlationbiometricsfingerprint verificationfingerprint identification
 Summary | Full Text:PDF(3.1MB)

Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms
Jun SAKIYAMA Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3009-3019
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
computer arithmetic algorithmsparallel countersmultipliersdatapathVLSIcircuit synthesis
 Summary | Full Text:PDF(905.4KB)

High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation
Kenji TAKITA Takafumi AOKI Yoshifumi SASAKI Tatsuo HIGUCHI Koji KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8  pp. 1925-1934
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
image registrationsubpixel registrationimage matchingphase-only correlationphase correlation
 Summary | Full Text:PDF(700.5KB)

Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8  pp. 2001-2010
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
multiple-valued logicsignal processorFPGAsFIR filters
 Summary | Full Text:PDF(2.9MB)

Fingerprint Restoration Using Digital Reaction-Diffusion System and Its Evaluation
Koichi ITO Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8  pp. 1916-1924
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
reaction-diffusion systempattern formationdigital signal processingdigital filtersfingerprint restoration
 Summary | Full Text:PDF(7.5MB)

Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design
Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/09/01
Vol. E85-A  No. 9  pp. 2061-2071
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
multiple-valued logicarithmetic circuitevolutionary computationgenetic algorithm (GA)
 Summary | Full Text:PDF(1.2MB)

Parallel Evolutionary Design of Constant-Coefficient Multipliers
Dingjun CHEN Takafumi AOKI Naofumi HOMMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2  pp. 508-512
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
evolutionary graph generationmultiplierPC clusterscanonical signed-digit (CSD) number representation
 Summary | Full Text:PDF(718.4KB)

Design of High-Radix VLSI Dividers without Quotient Selection Tables
Takafumi AOKI Kimihiko NAKAZAWA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2623-2631
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
computer arithmeticSRT divisionhigh-radix divisionsigned-digit number systemsVLSI
 Summary | Full Text:PDF(1.2MB)

Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--
Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2808-2810
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Synthesis
Keyword: 
multiple-valued logicarithmetic circuitsevolutionary computationgenetic algorithm
 Summary | Full Text:PDF(343.3KB)

Digital Reaction-Diffusion System--A Foundation of Bio-Inspired Texture Image Processing--
Koichi ITO Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8  pp. 1909-1918
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Image/Visual Signal Processing
Keyword: 
reaction-diffusion systempattern formationdigital signal processingdigital filters
 Summary | Full Text:PDF(4.4MB)

Evolutionary Synthesis of Fast Constant-Coefficient Multipliers
Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/09/25
Vol. E83-A  No. 9  pp. 1767-1777
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
circuit designcomputer arithmeticarithmetic circuitsevolvable hardwareevolutionary computation
 Summary | Full Text:PDF(982.5KB)

Radix-2-4-8 CORDIC for Fast Vector Rotation
Takafumi AOKI Ichiro KITAORI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6  pp. 1106-1114
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
computer arithmeticarithmetic circuitsCORDICVLSIdigital signal processing
 Summary | Full Text:PDF(1.2MB)

Pattern Formation in Reaction-Diffusion Enzyme Transistor Circuits
Masahiko HIRATSUKA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9  pp. 1809-1817
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
molecular computingmolecular devicesreaction-diffusion dynamicspattern formationnonlinear signal processingparallel processing
 Summary | Full Text:PDF(926.5KB)

Signed-Weight Arithmetic and Its Application to a Field-Programmable Digital Filter Architecture
Takafumi AOKI Yoshiki SAWADA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1687-1698
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Configurable Computing and Fault Tolerance
Keyword: 
computer arithmeticredundant number systemsdigital signal processingFIR filterFPGAs
 Summary | Full Text:PDF(2.7MB)

A Code-Division Multiplexing Technique for Efficient Data Transmission in VLSI Systems
Yasushi YUMINAKA Kazuhiko ITOH Yoshisato SASAKI Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1669-1677
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Non-Binary Architectures
Keyword: 
VLSI systemscode division multiplexingm-sequencenew paradigm computingspread-spectrum image processing
 Summary | Full Text:PDF(1.9MB)

FOREWORD
Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1597-1598
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(32.7KB)

Roundoff Error Analysis in the Decoding of Fractal Image Coding Using a Simplified State-Space Model
Choong Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/25
Vol. E82-A  No. 6  pp. 872-878
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))
Category: 
Keyword: 
fractal image codingiterated function systemroundoff errorstate-space approach
 Summary | Full Text:PDF(768KB)

Evolutionary Design of Arithmetic Circuits
Takafumi AOKI Naofumi HOMMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/05/25
Vol. E82-A  No. 5  pp. 798-806
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
circuit designcomputer arithmeticarithmetic circuitsevolvable hardwareevolutionary computation
 Summary | Full Text:PDF(758.6KB)

A Perfect-Reconstruction Encryption Scheme by Using Periodically Time-Varying Digital Filters
Xuedong YANG Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/01/25
Vol. E81-A  No. 1  pp. 192-196
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
perfect-reconstruction encryptionperiodically time-varying digital filtersfrequency scramble
 Summary | Full Text:PDF(296.2KB)

Analysis of Scaling-Factor-Quantization Error in Fractal Image Coding
Choong Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/12/25
Vol. E80-A  No. 12  pp. 2572-2580
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
fractal image codingiterated function systemsscaling-factor-quantization errorstate-space approach
 Summary | Full Text:PDF(790.3KB)

Design and Analysis of Multiwave Interconnection Networks for MCM-Based Parallel Processing
Takafumi AOKI Shinichi SHIONOYA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 935-940
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Concept Devices
Keyword: 
parallel processinginterconnection networksmessage-passing multiprocessor systemsmultichip module (MCM)optical interconnections
 Summary | Full Text:PDF(666.7KB)

State-Space Approach to Roundoff Error Analysis of Fractal Image Coding
Choong Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/01/25
Vol. E80-A  No. 1  pp. 159-165
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
fractal image codingiterated function systemsroundoff error analysisstate-space approach
 Summary | Full Text:PDF(776.1KB)

Evolutionary Digital Filtering Based on the Cloning and Mating Reproduction
Masahide ABE Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 370-373
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
adaptive digital filtersystem identificationevolution strategiesmulti-point searchnon-gradient search
 Summary | Full Text:PDF(325.7KB)

Design of Multiplierless 2-D State-Space Digital Filters over a Powers-of-Two Coefficient Space
Young-Ho LEE Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 374-377
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
multiplierless 2-D state-space digital filterspowers-of-twogenetic algorithmhigh-speed operation
 Summary | Full Text:PDF(313.3KB)

FOREWORD
Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/09/25
Vol. E77-A  No. 9  pp. 1415-1416
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(102.5KB)

Low-Power 8-Valued Cellular Array VLSI for High-Speed Image Processing
Takahiro HANYU Maho KUWAHARA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1042-1048
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
multiple-valued logicdynamic circuitssmall latencycellular arraytemplate matching
 Summary | Full Text:PDF(760.4KB)

FOREWORD
Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 935-936
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(115.6KB)

FOREWORD
Shuichi UENO Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 445-446
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(161.6KB)

A High-Density Multiple-Valued Content-Addressable Memory Based on One Transistor Cell
Satoshi ARAGAKI Takahiro HANYU Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1649-1656
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
content-addressable memorymultiple-valued logicfloating-gate MOSthreshold functionlogic-value conversionrelational search operation
 Summary | Full Text:PDF(608.8KB)

Design of Wave-Parallel Computing Architectures and Its Application to Massively Parallel Image Processing
Yasushi YUMINAKA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1133-1143
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
multiple-valued logicset-valued logicparallel processingfrequency multiplexing
 Summary | Full Text:PDF(1013.4KB)

Research Topics and Results on Digital Signal Processing
Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/07/25
Vol. E76-A  No. 7  pp. 1087-1096
Type of Manuscript:  Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I)
Category: 
Keyword: 
M-D digital filtermultiple-valued logic circuitssignal processor
 Summary | Full Text:PDF(945.3KB)

3-D Object Recognition System Based on 2-D Chain Code Matching
Takahiro HANYU Sungkun CHOI Michitaka KANEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 917-923
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Methods and Circuits for Signal Processing
Keyword: 
3-D object recognitionchain code sequencenormalizationfast fourier transform (FFT)chain code matching3-D measurement
 Summary | Full Text:PDF(580.1KB)

Unified Scheduling of High Performance Parallel VLSI Processors for Robotics
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 904-910
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Parallel Processor Scheduling
Keyword: 
minimum-latency architecturespecial-purpose VLSI processorparallel processingcommunication timebus interconnection network
 Summary | Full Text:PDF(514.9KB)

FOREWORD
Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5  pp. 525-526
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(138.1KB)

Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory
Saneaki TAMAKI Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5  pp. 548-554
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Logic Design
Keyword: 
multiple-valued codinglocally computable circuitunary operationpartition theoryclosed chain set
 Summary | Full Text:PDF(500.8KB)

Optical Multiplex Computing Based on Set-Valued Logic and Its Application to Parallel Sorting Networks
Shuichi MAEDA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5  pp. 605-615
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Optical Logic
Keyword: 
optical computingoptoelectronic integrated circuitsset-valued logicmultiple-valued logicparallel processing
 Summary | Full Text:PDF(1009.1KB)

Analysis of Multidimensional Linear Periodically Shift-Variant Digital Filters and Its Application to Secure Communication of Images
Masayuki KAWAMATA Sho MURAKOSHI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3  pp. 326-336
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
digital signal processingmultidimensional digital filterslinear shift-variant systemfrequency scramblesecure communication
 Summary | Full Text:PDF(829KB)

Rule-Programmable Multiple-Valued Matching VLSI Processor for Real-Time Rule-Based Systems
Takahiro HANYU Koichi TAKEDA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 472-479
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued encodingmultiple-valued pattern matchingfloating-gate MOS devicesprogrammable delta literalfully parallel processing
 Summary | Full Text:PDF(644.5KB)

Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation
Makoto HONDA Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 455-462
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued MOS current-mode circuitresidue number systemlatencyparallel processingrobot vision
 Summary | Full Text:PDF(737.7KB)

Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation
Takeshi KASUGA Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 428-435
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
robust-fault-tolerant arithmetic circuitbitonic sorter three-valued distributed codingsafetyscaler multiple-valued current-mode circuit
 Summary | Full Text:PDF(758.4KB)

Prospects of Multiple-Valued VLSI Processors
Takahiro HANYU Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 383-392
Type of Manuscript:  INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
submicron VLSIinterconnection delaymultiple-valued hardware algorithmparallel VLSI processorMVL arithmetic and logic circuits
 Summary | Full Text:PDF(981KB)

FOREWORD
Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 345-346
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(115KB)

Design of a Multiple-Valued VLSI Processor for Digital Control
Katsuhiko SHIMABUKURO Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/09/25
Vol. E75-D  No. 5  pp. 709-717
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
parallel-structure-based VLSI processorsigned-digit arithmetic systemmultiple-valued circuit technologybidirectional current-mode circuits
 Summary | Full Text:PDF(640.3KB)

Design of Three-Dimensional Digital Filters for Video Signal Processing via Decomposition of Magnitude Specifications
Masayuki KAWAMATA Takehiko KAGOSHIMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7  pp. 821-829
Type of Manuscript:  Special Section PAPER (Special Section on Multidimensional Signal Processing)
Category: Design and Implementation of Multidimensional Digital Filters
Keyword: 
designparallel separable 3-D digital filterreal time video signal processingdecomposition
 Summary | Full Text:PDF(701.7KB)

Design and Evaluation of Highly Prallel VLSI Processors for 2-D State-Space Digital Filters Using Hierarchical Behavioral Description Language and Synthesizer
Masayuki KAWAMATA Yasushi IWATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7  pp. 837-845
Type of Manuscript:  Special Section PAPER (Special Section on Multidimensional Signal Processing)
Category: Design and Implementation of Multidimensional Digital Filters
Keyword: 
two dimensional state-space digital filtersVLSI processorsdistributed arithmeticbehavioral description languagelogic synthesizer
 Summary | Full Text:PDF(685.8KB)

Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/06/25
Vol. E75-A  No. 6  pp. 712-719
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
Category: Robot Electronics
Keyword: 
minimum-delay-time architectureVLSI processor for roboticsparallel processingparallel communicationmultiple bus interconnection networks
 Summary | Full Text:PDF(555.1KB)

Highly Parallel Collision Detection Processor for Intelligent Robots
Michitaka KAMEYAMA Tadao AMADA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 398-404
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF(572.7KB)

A Special-Purpose LSI for Inverse Kinematics Computation
Michitaka KAMEYAMA Takao MATSUMOTO Hideki EGAMI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3829-3837
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Dedicated Processors
Keyword: 
 Summary | Full Text:PDF(853.6KB)

Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation
Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3819-3828
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Dedicated Processors
Keyword: 
 Summary | Full Text:PDF(822.5KB)

A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing
Takahiro HANYU Hiroto ISHII Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 918-928
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: ASIC
Keyword: 
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Controllability, Observability and Model Reduction of Separable Denominator M-D Systems
ZHAO Qiangfu Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/05/25
Vol. E71-E  No. 5  pp. 505-513
Type of Manuscript:  PAPER
Category: Systems and Control
Keyword: 
 Summary | Full Text:PDF(680.9KB)

A Unified Approach to the Minimization of Quantization Effects in Separable Denominator Multi-Dimensional Digital Filters
ZHAO Qingfu Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/11/25
Vol. E70-E  No. 11  pp. 1092-1095
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
 Summary | Full Text:PDF(243.4KB)

Minimization of Sensitivity of 2-D Systems and Its Relation to 2-D Balanced Realizations
Tao LIN Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/10/25
Vol. E70-E  No. 10  pp. 938-944
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
 Summary | Full Text:PDF(565.9KB)

Direct Design of Separable Denominator 3-D State-Space Digital Filters
ZHAO Qiangfu Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/04/25
Vol. E70-E  No. 4  pp. 411-421
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
 Summary | Full Text:PDF(722KB)

Limit Cycle-Free 2-D Separable Denominator Digital Filters under Any Constant Input Conditions
Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/04/25
Vol. E70-E  No. 4  pp. 373-375
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
 Summary | Full Text:PDF(200.6KB)

A New Property of Optimal Realizations of CRSD 2-D Digital Filters and Its Application to the Direct Spatial-Domain Design
ZHAO Qiangfu Masayuki KAWAMATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/10/25
Vol. E69-E  No. 10  pp. 1084-1092
Type of Manuscript:  PAPER
Category: System Theory
Keyword: 
 Summary | Full Text:PDF(717.7KB)

A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier
Michitaka KAMEYAMA Oluwole ADEGBENRO Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1985/01/25
Vol. E68-E  No. 1  pp. 14-21
Type of Manuscript:  PAPER
Category: Signal Processing
Keyword: 
 Summary | Full Text:PDF(538.7KB)