Tasuku NISHIHARA


Multi-Level Bounded Model Checking with Symbolic Counterexamples
Tasuku NISHIHARA Takeshi MATSUMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2  pp. 696-705
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
formal verificationbounded model checkingfinite state machine with datapathsymbolic simulation
 Summary | Full Text:PDF(1.4MB)

Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
Tasuku NISHIHARA Takeshi MATSUMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5  pp. 972-984
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Hardware Verification
Keyword: 
high-level synthesisbehavioral synthesisformal verificationequivalence checking
 Summary | Full Text:PDF(1022KB)